www.pudn.com > CLOCK.rar > Block.qsf

# Copyright (C) 1991-2007 Altera Corporation 
# Your use of Altera Corporation's design tools, logic functions  
# and other software and tools, and its AMPP partner logic  
# functions, and any output files from any of the foregoing  
# (including device programming or simulation files), and any  
# associated documentation or information are expressly subject  
# to the terms and conditions of the Altera Program License  
# Subscription Agreement, Altera MegaCore Function License  
# Agreement, or other applicable license agreement, including,  
# without limitation, that your use is for the sole purpose of  
# programming logic devices manufactured by Altera and sold by  
# Altera or its authorized distributors.  Please refer to the  
# applicable agreement for further details. 
 
 
# The default values for assignments are stored in the file 
#		Block_assignment_defaults.qdf 
# If this file doesn't exist, and for assignments not listed, see file 
#		assignment_defaults.qdf 
 
# Altera recommends that you do not modify this file. This 
# file is updated automatically by the Quartus II software 
# and any changes you make may be lost or overwritten. 
 
 
set_global_assignment -name FAMILY ACEX1K 
set_global_assignment -name DEVICE "EP1K100QC208-3" 
set_global_assignment -name TOP_LEVEL_ENTITY Block 
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 7.2 
set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:45:51  JUNE 15, 2008" 
set_global_assignment -name LAST_QUARTUS_VERSION 7.2 
set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_palace 
set_global_assignment -name BDF_FILE Block.bdf 
set_instance_assignment -name PARTITION_HIERARCHY no_file_for_top_partition -to | -section_id Top 
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top 
set_global_assignment -name PARTITION_COLOR 2147039 -section_id Top 
set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region" 
set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region" 
set_location_assignment PIN_15 -to CLK6 
set_location_assignment PIN_12 -to CLK5 
set_location_assignment PIN_11 -to CLK4 
set_location_assignment PIN_9 -to CLK3 
set_location_assignment PIN_8 -to CLK2 
set_location_assignment PIN_7 -to CLK1 
set_location_assignment PIN_142 -to date[3] 
set_location_assignment PIN_141 -to date[2] 
set_location_assignment PIN_140 -to date[1] 
set_location_assignment PIN_139 -to date[0] 
set_location_assignment PIN_132 -to hourl[3] 
set_location_assignment PIN_131 -to hourl[2] 
set_location_assignment PIN_128 -to hourl[1] 
set_location_assignment PIN_127 -to hourl[0] 
set_location_assignment PIN_126 -to hour0[3] 
set_location_assignment PIN_125 -to hour0[2] 
set_location_assignment PIN_122 -to hour0[1] 
set_location_assignment PIN_121 -to hour0[0] 
set_location_assignment PIN_120 -to minutel[3] 
set_location_assignment PIN_119 -to minutel[2] 
set_location_assignment PIN_116 -to minutel[1] 
set_location_assignment PIN_115 -to minutel[0] 
set_location_assignment PIN_114 -to minute0[3] 
set_location_assignment PIN_113 -to minute0[2] 
set_location_assignment PIN_45 -to minute0[1] 
set_location_assignment PIN_44 -to minute0[0] 
set_location_assignment PIN_41 -to secondl[3] 
set_location_assignment PIN_40 -to secondl[2] 
set_location_assignment PIN_39 -to secondl[1] 
set_location_assignment PIN_38 -to secondl[0] 
set_location_assignment PIN_37 -to second0[3] 
set_location_assignment PIN_36 -to second0[2] 
set_location_assignment PIN_31 -to second0[1] 
set_location_assignment PIN_30 -to second0[0] 
set_location_assignment PIN_29 -to diode[7] 
set_location_assignment PIN_28 -to diode[6] 
set_location_assignment PIN_27 -to diode[5] 
set_location_assignment PIN_26 -to diode[4] 
set_location_assignment PIN_25 -to diode[3] 
set_location_assignment PIN_24 -to diode[2] 
set_location_assignment PIN_18 -to diode[1] 
set_location_assignment PIN_17 -to diode[0] 
set_global_assignment -name VHDL_FILE clk_div.vhd 
set_location_assignment PIN_78 -to CLK 
set_global_assignment -name FITTER_EFFORT "STANDARD FIT" 
set_location_assignment PIN_58 -to RST0 
set_location_assignment PIN_85 -to RST1 
set_global_assignment -name VHDL_FILE class.vhd 
set_location_assignment PIN_148 -to alart_1 
set_location_assignment PIN_149 -to alart_2