www.pudn.com > eternityclock.rar > clocktop.syr
Release 9.2i - xst J.36
Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved.
--> Parameter TMPDIR set to ./xst/projnav.tmp
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--> Parameter xsthdpdir set to ./xst
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--> Reading design: clocktop.prj
TABLE OF CONTENTS
1) Synthesis Options Summary
2) HDL Compilation
3) Design Hierarchy Analysis
4) HDL Analysis
5) HDL Synthesis
5.1) HDL Synthesis Report
6) Advanced HDL Synthesis
6.1) Advanced HDL Synthesis Report
7) Low Level Synthesis
8) Partition Report
9) Final Report
9.1) Device utilization summary
9.2) Partition Resource Summary
9.3) TIMING REPORT
=========================================================================
* Synthesis Options Summary *
=========================================================================
---- Source Parameters
Input File Name : "clocktop.prj"
Input Format : mixed
Ignore Synthesis Constraint File : NO
---- Target Parameters
Output File Name : "clocktop"
Output Format : NGC
Target Device : xc3s400-4-pq208
---- Source Options
Top Module Name : clocktop
Automatic FSM Extraction : YES
FSM Encoding Algorithm : Auto
Safe Implementation : No
FSM Style : lut
RAM Extraction : Yes
RAM Style : Auto
ROM Extraction : Yes
Mux Style : Auto
Decoder Extraction : YES
Priority Encoder Extraction : YES
Shift Register Extraction : YES
Logical Shifter Extraction : YES
XOR Collapsing : YES
ROM Style : Auto
Mux Extraction : YES
Resource Sharing : YES
Asynchronous To Synchronous : NO
Multiplier Style : auto
Automatic Register Balancing : No
---- Target Options
Add IO Buffers : YES
Global Maximum Fanout : 500
Add Generic Clock Buffer(BUFG) : 8
Register Duplication : YES
Slice Packing : YES
Optimize Instantiated Primitives : NO
Use Clock Enable : Yes
Use Synchronous Set : Yes
Use Synchronous Reset : Yes
Pack IO Registers into IOBs : auto
Equivalent register Removal : YES
---- General Options
Optimization Goal : Speed
Optimization Effort : 1
Library Search Order : clocktop.lso
Keep Hierarchy : NO
RTL Output : Yes
Global Optimization : AllClockNets
Read Cores : YES
Write Timing Constraints : NO
Cross Clock Analysis : NO
Hierarchy Separator : /
Bus Delimiter : <>
Case Specifier : maintain
Slice Utilization Ratio : 100
BRAM Utilization Ratio : 100
Verilog 2001 : YES
Auto BRAM Packing : NO
Slice Utilization Ratio Delta : 5
=========================================================================
=========================================================================
* HDL Compilation *
=========================================================================
Compiling verilog file "shake.v" in library work
Compiling verilog file "clockcore.v" in library work
Module compiled
Compiling verilog file "clocktop.v" in library work
Module compiled
Module compiled
No errors in compilation
Analysis of file <"clocktop.prj"> succeeded.
=========================================================================
* Design Hierarchy Analysis *
=========================================================================
Analyzing hierarchy for module in library .
Analyzing hierarchy for module in library with parameters.
shaketime = "011110100001001000000"
Analyzing hierarchy for module in library with parameters.
SEC = "10011111111111111111111111"
d0 = "10001000"
d1 = "11011011"
d2 = "10100010"
d3 = "10010010"
d4 = "11010001"
d5 = "10010100"
d6 = "10000100"
d7 = "11011010"
d8 = "10000000"
d9 = "10010000"
dnone = "00001111"
dp = "01111111"
=========================================================================
* HDL Analysis *
=========================================================================
Analyzing top module .
Module is correct for synthesis.
Analyzing module in library .
shaketime = 21'b011110100001001000000
Module is correct for synthesis.
Analyzing module in library .
SEC = 26'b10011111111111111111111111
d0 = 8'b10001000
d1 = 8'b11011011
d2 = 8'b10100010
d3 = 8'b10010010
d4 = 8'b11010001
d5 = 8'b10010100
d6 = 8'b10000100
d7 = 8'b11011010
d8 = 8'b10000000
d9 = 8'b10010000
dnone = 8'b00001111
dp = 8'b01111111
WARNING:Xst:905 - "clockcore.v" line 163: The signals are missing in the sensitivity list of always block.
Module is correct for synthesis.
=========================================================================
* HDL Synthesis *
=========================================================================
Performing bidirectional port resolution...
Synthesizing Unit .
Related source file is "shake.v".
WARNING:Xst:1780 - Signal is never used or assigned.
Found 1-bit register for signal .
Found 1-bit register for signal .
Found 1-bit register for signal .
Found 1-bit register for signal .
Found 21-bit up counter for signal .
Summary:
inferred 1 Counter(s).
inferred 4 D-type flip-flop(s).
Unit synthesized.
Synthesizing Unit .
Related source file is "clockcore.v".
WARNING:Xst:646 - Signal > is assigned but never used.
WARNING:Xst:646 - Signal > is assigned but never used.
WARNING:Xst:646 - Signal > is assigned but never used.
Found finite state machine for signal .
-----------------------------------------------------------------------
| States | 4 |
| Transitions | 4 |
| Inputs | 0 |
| Outputs | 3 |
| Clock | b4 (falling_edge) |
| Reset | b1 (negative) |
| Reset type | asynchronous |
| Reset State | 00 |
| Encoding | automatic |
| Implementation | LUT |
-----------------------------------------------------------------------
Found finite state machine for signal .
-----------------------------------------------------------------------
| States | 5 |
| Transitions | 6 |
| Inputs | 1 |
| Outputs | 5 |
| Clock | b3 (falling_edge) |
| Reset | b1 (negative) |
| Reset type | asynchronous |
| Reset State | 000 |
| Encoding | automatic |
| Implementation | LUT |
-----------------------------------------------------------------------
WARNING:Xst:2734 - Property "use_dsp48" is not applicable for this technology.
Found 16x1-bit ROM for signal .
Found 8-bit 16-to-1 multiplexer for signal .
Found 1-bit xor3 for signal .
Found 4-bit up counter for signal >.
Found 4-bit register for signal >.
Found 4-bit adder for signal created at line 323.
Found 4-bit comparator equal for signal created at line 318.
Found 4-bit comparator equal for signal created at line 318.
Found 4-bit comparator not equal for signal created at line 318.
Found 4-bit comparator not equal for signal created at line 318.
Found 1-bit register for signal .
Found 4-bit 16-to-1 multiplexer for signal .
Found 26-bit up counter for signal .
Found 1-bit register for signal .
Found 4-bit up counter for signal >.
Found 4-bit register for signal >.
Found 4-bit adder for signal created at line 309.
Found 1-bit xor2 for signal created at line 85.
Found 1-bit register for signal .
Found 4-bit register for signal >.
Found 4-bit up counter for signal >.
Found 1-bit register for signal .
Found 4-bit up counter for signal >.
Found 4-bit register for signal >.
Found 4-bit adder for signal created at line 341.
Found 4-bit adder for signal created at line 284.
Found 4-bit adder for signal created at line 295.
Found 1-of-4 decoder for signal .
Found 11-bit up counter for signal .
Found 1-bit register for signal .
Found 4-bit register for signal >.
Found 4-bit up counter for signal >.
Found 4-bit up counter for signal .
Found 1-bit register for signal .
Found 1-bit register for signal .
Found 1-bit register for signal .
Found 1-bit register for signal .
Summary:
inferred 2 Finite State Machine(s).
inferred 1 ROM(s).
inferred 11 Counter(s).
inferred 13 D-type flip-flop(s).
inferred 5 Adder/Subtractor(s).
inferred 4 Comparator(s).
inferred 12 Multiplexer(s).
inferred 1 Decoder(s).
inferred 1 Xor(s).
Unit synthesized.
Synthesizing Unit .
Related source file is "clocktop.v".
Unit synthesized.
=========================================================================
HDL Synthesis Report
Macro Statistics
# ROMs : 1
16x1-bit ROM : 1
# Adders/Subtractors : 5
4-bit adder : 5
# Counters : 12
11-bit up counter : 1
21-bit up counter : 1
26-bit up counter : 1
4-bit up counter : 9
# Registers : 18
1-bit register : 13
4-bit register : 5
# Comparators : 4
4-bit comparator equal : 2
4-bit comparator not equal : 2
# Multiplexers : 2
4-bit 16-to-1 multiplexer : 1
8-bit 16-to-1 multiplexer : 1
# Decoders : 1
1-of-4 decoder : 1
# Xors : 2
1-bit xor2 : 1
1-bit xor3 : 1
=========================================================================
=========================================================================
* Advanced HDL Synthesis *
=========================================================================
Analyzing FSM for best encoding.
Optimizing FSM on signal with gray encoding.
-------------------
State | Encoding
-------------------
000 | 000
100 | 001
101 | 011
110 | 010
111 | 110
-------------------
Analyzing FSM for best encoding.
Optimizing FSM on signal with gray encoding.
-------------------
State | Encoding
-------------------
00 | 00
01 | 01
10 | 11
11 | 10
-------------------
Loading device for application Rf_Device from file '3s400.nph' in environment E:\Xilinx92i.
=========================================================================
Advanced HDL Synthesis Report
Macro Statistics
# FSMs : 2
# ROMs : 1
16x1-bit ROM : 1
# Adders/Subtractors : 5
4-bit adder : 5
# Counters : 12
11-bit up counter : 1
21-bit up counter : 1
26-bit up counter : 1
4-bit up counter : 9
# Registers : 38
Flip-Flops : 38
# Comparators : 4
4-bit comparator equal : 2
4-bit comparator not equal : 2
# Multiplexers : 2
4-bit 16-to-1 multiplexer : 1
8-bit 16-to-1 multiplexer : 1
# Decoders : 1
1-of-4 decoder : 1
# Xors : 2
1-bit xor2 : 1
1-bit xor3 : 1
=========================================================================
=========================================================================
* Low Level Synthesis *
=========================================================================
Optimizing unit ...
Optimizing unit ...
Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block clocktop, actual ratio is 4.
Final Macro Processing ...
=========================================================================
Final Register Report
Macro Statistics
# Registers : 132
Flip-Flops : 132
=========================================================================
=========================================================================
* Partition Report *
=========================================================================
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
=========================================================================
* Final Report *
=========================================================================
Final Results
RTL Top Level Output File Name : clocktop.ngr
Top Level Output File Name : clocktop
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : NO
Design Statistics
# IOs : 17
Cell Usage :
# BELS : 464
# GND : 1
# INV : 16
# LUT1 : 55
# LUT2 : 66
# LUT2_D : 1
# LUT2_L : 1
# LUT3 : 58
# LUT3_L : 2
# LUT4 : 107
# LUT4_D : 10
# MUXCY : 68
# MUXF5 : 19
# MUXF6 : 4
# VCC : 1
# XORCY : 55
# FlipFlops/Latches : 132
# FDC : 68
# FDC_1 : 5
# FDCE : 42
# FDP : 3
# FDPE : 14
# Clock Buffers : 1
# BUFGP : 1
# IO Buffers : 16
# IBUF : 4
# OBUF : 12
=========================================================================
Device utilization summary:
---------------------------
Selected Device : 3s400pq208-4
Number of Slices: 167 out of 3584 4%
Number of Slice Flip Flops: 132 out of 7168 1%
Number of 4 input LUTs: 316 out of 7168 4%
Number of IOs: 17
Number of bonded IOBs: 17 out of 141 12%
Number of GCLKs: 1 out of 8 12%
---------------------------
Partition Resource Summary:
---------------------------
No Partitions were found in this design.
---------------------------
=========================================================================
TIMING REPORT
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.
Clock Information:
------------------
-------------------------------------------+-------------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-------------------------------------------+-------------------------------+-------+
shake/sample | NONE(shake/noshakeb4) | 3 |
clk | BUFGP | 60 |
clockkernel/y4buf(clockkernel/y4buf1:O) | NONE(*)(clockkernel/year_3_0) | 4 |
clockkernel/y3buf(clockkernel/y3buf1:O) | NONE(*)(clockkernel/year_2_3) | 5 |
clockkernel/y1buf(clockkernel/y1buf1:O) | NONE(*)(clockkernel/year_0_1) | 5 |
clockkernel/moncbuf(clockkernel/moncbuf1:O)| NONE(*)(clockkernel/month_1_0)| 9 |
clockkernel/y2buf(clockkernel/y2buf1:O) | NONE(*)(clockkernel/year_1_0) | 5 |
clockkernel/hclkbuf(clockkernel/hclkbuf1:O)| NONE(*)(clockkernel/hour_0_2) | 9 |
clockkernel/mclkbuf(clockkernel/mclkbuf1:O)| NONE(*)(clockkernel/min_1_1) | 9 |
clockkernel/daycbuf(clockkernel/daycbuf1:O)| NONE(*)(clockkernel/day_0_3) | 9 |
clockkernel/sclkbuf(clockkernel/sclkbuf1:O)| NONE(*)(clockkernel/mclk) | 9 |
shake/noshakeb4 | NONE(clockkernel/screen_FFd2) | 2 |
shake/noshakeb3 | NONE(clockkernel/state_FFd1) | 3 |
-------------------------------------------+-------------------------------+-------+
(*) These 9 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.
Asynchronous Control Signals Information:
----------------------------------------
-----------------------------------+------------------------+-------+
Control Signal | Buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
b1_inv(clockkernel/b1_inv1_INV_0:O)| NONE(shake/noshakeb4) | 132 |
-----------------------------------+------------------------+-------+
Timing Summary:
---------------
Speed Grade: -4
Minimum period: 7.178ns (Maximum Frequency: 139.315MHz)
Minimum input arrival time before clock: 2.791ns
Maximum output required time after clock: 15.296ns
Maximum combinational path delay: No path found
Timing Detail:
--------------
All values displayed in nanoseconds (ns)
=========================================================================
Timing constraint: Default period analysis for Clock 'clk'
Clock period: 7.113ns (frequency: 140.588MHz)
Total number of paths / destination ports: 1812 / 60
-------------------------------------------------------------------------
Delay: 7.113ns (Levels of Logic = 27)
Source: clockkernel/divcounter_1 (FF)
Destination: clockkernel/divcounter_25 (FF)
Source Clock: clk rising
Destination Clock: clk rising
Data Path: clockkernel/divcounter_1 to clockkernel/divcounter_25
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDC:C->Q 2 0.720 1.216 clockkernel/divcounter_1 (clockkernel/divcounter_1)
LUT1:I0->O 1 0.551 0.000 clockkernel/Mcount_divcounter_cy<1>_rt (clockkernel/Mcount_divcounter_cy<1>_rt)
MUXCY:S->O 1 0.500 0.000 clockkernel/Mcount_divcounter_cy<1> (clockkernel/Mcount_divcounter_cy<1>)
MUXCY:CI->O 1 0.064 0.000 clockkernel/Mcount_divcounter_cy<2> (clockkernel/Mcount_divcounter_cy<2>)
MUXCY:CI->O 1 0.064 0.000 clockkernel/Mcount_divcounter_cy<3> (clockkernel/Mcount_divcounter_cy<3>)
MUXCY:CI->O 1 0.064 0.000 clockkernel/Mcount_divcounter_cy<4> (clockkernel/Mcount_divcounter_cy<4>)
MUXCY:CI->O 1 0.064 0.000 clockkernel/Mcount_divcounter_cy<5> (clockkernel/Mcount_divcounter_cy<5>)
MUXCY:CI->O 1 0.064 0.000 clockkernel/Mcount_divcounter_cy<6> (clockkernel/Mcount_divcounter_cy<6>)
MUXCY:CI->O 1 0.064 0.000 clockkernel/Mcount_divcounter_cy<7> (clockkernel/Mcount_divcounter_cy<7>)
MUXCY:CI->O 1 0.064 0.000 clockkernel/Mcount_divcounter_cy<8> (clockkernel/Mcount_divcounter_cy<8>)
MUXCY:CI->O 1 0.064 0.000 clockkernel/Mcount_divcounter_cy<9> (clockkernel/Mcount_divcounter_cy<9>)
MUXCY:CI->O 1 0.064 0.000 clockkernel/Mcount_divcounter_cy<10> (clockkernel/Mcount_divcounter_cy<10>)
MUXCY:CI->O 1 0.064 0.000 clockkernel/Mcount_divcounter_cy<11> (clockkernel/Mcount_divcounter_cy<11>)
MUXCY:CI->O 1 0.064 0.000 clockkernel/Mcount_divcounter_cy<12> (clockkernel/Mcount_divcounter_cy<12>)
MUXCY:CI->O 1 0.064 0.000 clockkernel/Mcount_divcounter_cy<13> (clockkernel/Mcount_divcounter_cy<13>)
MUXCY:CI->O 1 0.064 0.000 clockkernel/Mcount_divcounter_cy<14> (clockkernel/Mcount_divcounter_cy<14>)
MUXCY:CI->O 1 0.064 0.000 clockkernel/Mcount_divcounter_cy<15> (clockkernel/Mcount_divcounter_cy<15>)
MUXCY:CI->O 1 0.064 0.000 clockkernel/Mcount_divcounter_cy<16> (clockkernel/Mcount_divcounter_cy<16>)
MUXCY:CI->O 1 0.064 0.000 clockkernel/Mcount_divcounter_cy<17> (clockkernel/Mcount_divcounter_cy<17>)
MUXCY:CI->O 1 0.064 0.000 clockkernel/Mcount_divcounter_cy<18> (clockkernel/Mcount_divcounter_cy<18>)
MUXCY:CI->O 1 0.064 0.000 clockkernel/Mcount_divcounter_cy<19> (clockkernel/Mcount_divcounter_cy<19>)
MUXCY:CI->O 1 0.064 0.000 clockkernel/Mcount_divcounter_cy<20> (clockkernel/Mcount_divcounter_cy<20>)
MUXCY:CI->O 1 0.064 0.000 clockkernel/Mcount_divcounter_cy<21> (clockkernel/Mcount_divcounter_cy<21>)
MUXCY:CI->O 1 0.064 0.000 clockkernel/Mcount_divcounter_cy<22> (clockkernel/Mcount_divcounter_cy<22>)
MUXCY:CI->O 1 0.064 0.000 clockkernel/Mcount_divcounter_cy<23> (clockkernel/Mcount_divcounter_cy<23>)
MUXCY:CI->O 0 0.064 0.000 clockkernel/Mcount_divcounter_cy<24> (clockkernel/Mcount_divcounter_cy<24>)
XORCY:CI->O 1 0.904 0.996 clockkernel/Mcount_divcounter_xor<25> (clockkernel/Result<25>)
LUT2:I1->O 1 0.551 0.000 clockkernel/Mcount_divcounter_eqn_251 (clockkernel/Mcount_divcounter_eqn_25)
FDC:D 0.203 clockkernel/divcounter_25
----------------------------------------
Total 7.113ns (4.901ns logic, 2.212ns route)
(68.9% logic, 31.1% route)
=========================================================================
Timing constraint: Default period analysis for Clock 'clockkernel/y4buf'
Clock period: 3.196ns (frequency: 312.891MHz)
Total number of paths / destination ports: 12 / 4
-------------------------------------------------------------------------
Delay: 3.196ns (Levels of Logic = 1)
Source: clockkernel/year_3_0 (FF)
Destination: clockkernel/year_3_0 (FF)
Source Clock: clockkernel/y4buf rising
Destination Clock: clockkernel/y4buf rising
Data Path: clockkernel/year_3_0 to clockkernel/year_3_0
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDCE:C->Q 5 0.720 0.921 clockkernel/year_3_0 (clockkernel/year_3_0)
INV:I->O 1 0.551 0.801 clockkernel/Mcount_year_3_xor<0>11_INV_0 (clockkernel/Mcount_year_3)
FDCE:D 0.203 clockkernel/year_3_0
----------------------------------------
Total 3.196ns (1.474ns logic, 1.722ns route)
(46.1% logic, 53.9% route)
=========================================================================
Timing constraint: Default period analysis for Clock 'clockkernel/y3buf'
Clock period: 3.278ns (frequency: 305.064MHz)
Total number of paths / destination ports: 16 / 5
-------------------------------------------------------------------------
Delay: 3.278ns (Levels of Logic = 1)
Source: clockkernel/year_2_0 (FF)
Destination: clockkernel/year_2_0 (FF)
Source Clock: clockkernel/y3buf rising
Destination Clock: clockkernel/y3buf rising
Data Path: clockkernel/year_2_0 to clockkernel/year_2_0
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDCE:C->Q 6 0.720 1.003 clockkernel/year_2_0 (clockkernel/year_2_0)
INV:I->O 1 0.551 0.801 clockkernel/Mcount_year_2_xor<0>11_INV_0 (clockkernel/Mcount_year_2)
FDCE:D 0.203 clockkernel/year_2_0
----------------------------------------
Total 3.278ns (1.474ns logic, 1.804ns route)
(45.0% logic, 55.0% route)
=========================================================================
Timing constraint: Default period analysis for Clock 'clockkernel/y1buf'
Clock period: 4.154ns (frequency: 240.732MHz)
Total number of paths / destination ports: 16 / 5
-------------------------------------------------------------------------
Delay: 4.154ns (Levels of Logic = 2)
Source: clockkernel/year_0_2 (FF)
Destination: clockkernel/year2c (FF)
Source Clock: clockkernel/y1buf rising
Destination Clock: clockkernel/y1buf rising
Data Path: clockkernel/year_0_2 to clockkernel/year2c
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDPE:C->Q 5 0.720 1.260 clockkernel/year_0_2 (clockkernel/year_0_2)
LUT3:I0->O 1 0.551 0.869 clockkernel/year2c_mux0000_SW0 (N191)
LUT4:I2->O 1 0.551 0.000 clockkernel/year2c_mux0000 (clockkernel/year2c_mux0000)
FDC:D 0.203 clockkernel/year2c
----------------------------------------
Total 4.154ns (2.025ns logic, 2.129ns route)
(48.7% logic, 51.3% route)
=========================================================================
Timing constraint: Default period analysis for Clock 'clockkernel/moncbuf'
Clock period: 5.855ns (frequency: 170.794MHz)
Total number of paths / destination ports: 104 / 13
-------------------------------------------------------------------------
Delay: 5.855ns (Levels of Logic = 3)
Source: clockkernel/month_0_2 (FF)
Destination: clockkernel/month_1_2 (FF)
Source Clock: clockkernel/moncbuf rising
Destination Clock: clockkernel/moncbuf rising
Data Path: clockkernel/month_0_2 to clockkernel/month_1_2
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDPE:C->Q 5 0.720 1.260 clockkernel/month_0_2 (clockkernel/month_0_2)
LUT4_D:I0->O 5 0.551 1.116 clockkernel/feb11 (clockkernel/month_1_cmp_eq0001)
LUT2:I1->O 2 0.551 0.903 clockkernel/month_1_and00001 (clockkernel/month_1_and0000)
LUT4:I3->O 1 0.551 0.000 clockkernel/month_0_mux0000<2>1 (clockkernel/month_0_mux0000<2>)
FDPE:D 0.203 clockkernel/month_0_1
----------------------------------------
Total 5.855ns (2.576ns logic, 3.279ns route)
(44.0% logic, 56.0% route)
=========================================================================
Timing constraint: Default period analysis for Clock 'clockkernel/y2buf'
Clock period: 3.341ns (frequency: 299.312MHz)
Total number of paths / destination ports: 16 / 5
-------------------------------------------------------------------------
Delay: 3.341ns (Levels of Logic = 1)
Source: clockkernel/year_1_0 (FF)
Destination: clockkernel/year_1_0 (FF)
Source Clock: clockkernel/y2buf rising
Destination Clock: clockkernel/y2buf rising
Data Path: clockkernel/year_1_0 to clockkernel/year_1_0
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDCE:C->Q 7 0.720 1.066 clockkernel/year_1_0 (clockkernel/year_1_0)
INV:I->O 1 0.551 0.801 clockkernel/Mcount_year_1_xor<0>11_INV_0 (clockkernel/Mcount_year_1)
FDCE:D 0.203 clockkernel/year_1_0
----------------------------------------
Total 3.341ns (1.474ns logic, 1.867ns route)
(44.1% logic, 55.9% route)
=========================================================================
Timing constraint: Default period analysis for Clock 'clockkernel/hclkbuf'
Clock period: 5.923ns (frequency: 168.833MHz)
Total number of paths / destination ports: 120 / 13
-------------------------------------------------------------------------
Delay: 5.923ns (Levels of Logic = 3)
Source: clockkernel/hour_1_3 (FF)
Destination: clockkernel/hour_1_2 (FF)
Source Clock: clockkernel/hclkbuf rising
Destination Clock: clockkernel/hclkbuf rising
Data Path: clockkernel/hour_1_3 to clockkernel/hour_1_2
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDCE:C->Q 3 0.720 1.246 clockkernel/hour_1_3 (clockkernel/hour_1_3)
LUT4:I0->O 6 0.551 1.198 clockkernel/hour_1_cmp_eq00001 (clockkernel/hour_1_cmp_eq0000)
LUT2:I1->O 2 0.551 0.903 clockkernel/hour_1_and00001 (clockkernel/hour_1_and0000)
LUT4:I3->O 1 0.551 0.000 clockkernel/hour_0_mux0000<2>1 (clockkernel/hour_0_mux0000<2>)
FDCE:D 0.203 clockkernel/hour_0_1
----------------------------------------
Total 5.923ns (2.576ns logic, 3.347ns route)
(43.5% logic, 56.5% route)
=========================================================================
Timing constraint: Default period analysis for Clock 'clockkernel/mclkbuf'
Clock period: 7.161ns (frequency: 139.645MHz)
Total number of paths / destination ports: 89 / 9
-------------------------------------------------------------------------
Delay: 7.161ns (Levels of Logic = 4)
Source: clockkernel/min_1_1 (FF)
Destination: clockkernel/hclk (FF)
Source Clock: clockkernel/mclkbuf rising
Destination Clock: clockkernel/mclkbuf rising
Data Path: clockkernel/min_1_1 to clockkernel/hclk
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDCE:C->Q 7 0.720 1.405 clockkernel/min_1_1 (clockkernel/min_1_1)
LUT2:I0->O 1 0.551 0.869 clockkernel/Madd_mux0001_addsub0000_cy<1>11 (clockkernel/Madd_mux0001_addsub0000_cy<1>)
LUT4:I2->O 3 0.551 0.933 clockkernel/_mux0001<3>1 (clockkernel/_mux0001<3>)
LUT4_D:I3->O 1 0.551 0.827 clockkernel/min_1_cmp_eq0000_SW0 (N359)
LUT4:I3->O 1 0.551 0.000 clockkernel/hclk_mux0000 (clockkernel/hclk_mux0000)
FDC:D 0.203 clockkernel/hclk
----------------------------------------
Total 7.161ns (3.127ns logic, 4.034ns route)
(43.7% logic, 56.3% route)
=========================================================================
Timing constraint: Default period analysis for Clock 'clockkernel/daycbuf'
Clock period: 6.700ns (frequency: 149.254MHz)
Total number of paths / destination ports: 136 / 13
-------------------------------------------------------------------------
Delay: 6.700ns (Levels of Logic = 4)
Source: clockkernel/day_1_0 (FF)
Destination: clockkernel/day_1_2 (FF)
Source Clock: clockkernel/daycbuf rising
Destination Clock: clockkernel/daycbuf rising
Data Path: clockkernel/day_1_0 to clockkernel/day_1_2
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDCE:C->Q 6 0.720 1.198 clockkernel/day_1_0 (clockkernel/day_1_0)
LUT2_L:I1->LO 1 0.551 0.126 clockkernel/day_1_cmp_eq00004_SW0 (N302)
LUT4:I3->O 8 0.551 1.422 clockkernel/day_1_cmp_eq00004 (clockkernel/day_1_cmp_eq0000)
LUT2_D:I0->O 1 0.551 0.827 clockkernel/day_1_and00001 (clockkernel/day_1_and0000)
LUT4:I3->O 1 0.551 0.000 clockkernel/Mcount_day_1_xor<2>11 (clockkernel/Mcount_day_16)
FDCE:D 0.203 clockkernel/day_1_2
----------------------------------------
Total 6.700ns (3.127ns logic, 3.573ns route)
(46.7% logic, 53.3% route)
=========================================================================
Timing constraint: Default period analysis for Clock 'clockkernel/sclkbuf'
Clock period: 7.178ns (frequency: 139.315MHz)
Total number of paths / destination ports: 90 / 9
-------------------------------------------------------------------------
Delay: 7.178ns (Levels of Logic = 4)
Source: clockkernel/sec_1_1 (FF)
Destination: clockkernel/mclk (FF)
Source Clock: clockkernel/sclkbuf rising
Destination Clock: clockkernel/sclkbuf rising
Data Path: clockkernel/sec_1_1 to clockkernel/mclk
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDCE:C->Q 8 0.720 1.422 clockkernel/sec_1_1 (clockkernel/sec_1_1)
LUT2:I0->O 1 0.551 0.869 clockkernel/Madd_mux0000_addsub0000_cy<1>11 (clockkernel/Madd_mux0000_addsub0000_cy<1>)
LUT4:I2->O 3 0.551 0.933 clockkernel/_mux0000<3>1 (clockkernel/_mux0000<3>)
LUT4_D:I3->O 1 0.551 0.827 clockkernel/sec_1_cmp_eq0000_SW0 (N357)
LUT4:I3->O 1 0.551 0.000 clockkernel/mclk_mux0000 (clockkernel/mclk_mux0000)
FDC:D 0.203 clockkernel/mclk
----------------------------------------
Total 7.178ns (3.127ns logic, 4.051ns route)
(43.6% logic, 56.4% route)
=========================================================================
Timing constraint: Default period analysis for Clock 'shake/noshakeb4'
Clock period: 3.875ns (frequency: 258.064MHz)
Total number of paths / destination ports: 2 / 2
-------------------------------------------------------------------------
Delay: 3.875ns (Levels of Logic = 1)
Source: clockkernel/screen_FFd1 (FF)
Destination: clockkernel/screen_FFd2 (FF)
Source Clock: shake/noshakeb4 falling
Destination Clock: shake/noshakeb4 falling
Data Path: clockkernel/screen_FFd1 to clockkernel/screen_FFd2
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDC_1:C->Q 22 0.720 1.600 clockkernel/screen_FFd1 (clockkernel/screen_FFd1)
INV:I->O 1 0.551 0.801 clockkernel/screen_FFd2-In1_INV_0 (clockkernel/screen_FFd2-In)
FDC_1:D 0.203 clockkernel/screen_FFd2
----------------------------------------
Total 3.875ns (1.474ns logic, 2.401ns route)
(38.0% logic, 62.0% route)
=========================================================================
Timing constraint: Default period analysis for Clock 'shake/noshakeb3'
Clock period: 3.790ns (frequency: 263.852MHz)
Total number of paths / destination ports: 7 / 3
-------------------------------------------------------------------------
Delay: 3.790ns (Levels of Logic = 1)
Source: clockkernel/state_FFd2 (FF)
Destination: clockkernel/state_FFd3 (FF)
Source Clock: shake/noshakeb3 falling
Destination Clock: shake/noshakeb3 falling
Data Path: clockkernel/state_FFd2 to clockkernel/state_FFd3
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDC_1:C->Q 21 0.720 1.515 clockkernel/state_FFd2 (clockkernel/state_FFd2)
INV:I->O 1 0.551 0.801 clockkernel/state_FFd3-In1_INV_0 (clockkernel/state_FFd3-In)
FDC_1:D 0.203 clockkernel/state_FFd3
----------------------------------------
Total 3.790ns (1.474ns logic, 2.316ns route)
(38.9% logic, 61.1% route)
=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'shake/sample'
Total number of paths / destination ports: 6 / 3
-------------------------------------------------------------------------
Offset: 2.791ns (Levels of Logic = 2)
Source: b3 (PAD)
Destination: shake/noshakeb2 (FF)
Destination Clock: shake/sample rising
Data Path: b3 to shake/noshakeb2
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 2 0.821 1.216 b3_IBUF (b3_IBUF)
LUT2:I0->O 1 0.551 0.000 shake/noshakeb3_mux00001 (shake/noshakeb3_mux0000)
FDP:D 0.203 shake/noshakeb3
----------------------------------------
Total 2.791ns (1.575ns logic, 1.216ns route)
(56.4% logic, 43.6% route)
=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'shake/noshakeb4'
Total number of paths / destination ports: 225 / 11
-------------------------------------------------------------------------
Offset: 14.614ns (Levels of Logic = 5)
Source: clockkernel/screen_FFd1 (FF)
Destination: N<7> (PAD)
Source Clock: shake/noshakeb4 falling
Data Path: clockkernel/screen_FFd1 to N<7>
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDC_1:C->Q 22 0.720 1.939 clockkernel/screen_FFd1 (clockkernel/screen_FFd1)
LUT2:I0->O 4 0.551 0.917 clockkernel/screen_or00011 (clockkernel/screen_or0001)
MUXF6:S->O 1 0.649 0.869 clockkernel/Mmux_dispdata_6_f6_0 (clockkernel/Mmux_dispdata_6_f61)
LUT3:I2->O 8 0.551 1.422 clockkernel/screen_or0000111 (clockkernel/dispdata<1>)
LUT4:I0->O 1 0.551 0.801 clockkernel/Mmux_N31 (N_2_OBUF)
OBUF:I->O 5.644 N_2_OBUF (N<2>)
----------------------------------------
Total 14.614ns (8.666ns logic, 5.948ns route)
(59.3% logic, 40.7% route)
=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
Total number of paths / destination ports: 351 / 12
-------------------------------------------------------------------------
Offset: 15.296ns (Levels of Logic = 6)
Source: clockkernel/scan_9 (FF)
Destination: N<7> (PAD)
Source Clock: clk rising
Data Path: clockkernel/scan_9 to N<7>
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDC:C->Q 34 0.720 2.204 clockkernel/scan_9 (clockkernel/scan_9)
LUT3:I0->O 2 0.551 0.945 clockkernel/scan<9>821 (clockkernel/scan<9>_mmx_out2)
LUT4:I2->O 1 0.551 0.000 clockkernel/Mmux_dispdata_5_f5_0_F (N444)
MUXF5:I0->O 1 0.360 0.996 clockkernel/Mmux_dispdata_5_f5_0 (clockkernel/Mmux_dispdata_5_f51)
LUT3:I1->O 8 0.551 1.422 clockkernel/screen_or0000111 (clockkernel/dispdata<1>)
LUT4:I0->O 1 0.551 0.801 clockkernel/Mmux_N31 (N_2_OBUF)
OBUF:I->O 5.644 N_2_OBUF (N<2>)
----------------------------------------
Total 15.296ns (8.928ns logic, 6.368ns route)
(58.4% logic, 41.6% route)
=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clockkernel/mclkbuf'
Total number of paths / destination ports: 124 / 8
-------------------------------------------------------------------------
Offset: 14.394ns (Levels of Logic = 6)
Source: clockkernel/min_1_0 (FF)
Destination: N<5> (PAD)
Source Clock: clockkernel/mclkbuf rising
Data Path: clockkernel/min_1_0 to N<5>
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDPE:C->Q 9 0.720 1.319 clockkernel/min_1_0 (clockkernel/min_1_0)
LUT3:I1->O 2 0.551 0.945 clockkernel/scan<9>831 (clockkernel/scan<9>_mmx_out3)
LUT4:I2->O 1 0.551 0.000 clockkernel/Mmux_dispdata_5_f5_F (N442)
MUXF5:I0->O 1 0.360 0.996 clockkernel/Mmux_dispdata_5_f5 (clockkernel/Mmux_dispdata_5_f5)
LUT3:I1->O 7 0.551 1.405 clockkernel/screen_or000011 (clockkernel/dispdata<0>)
LUT4:I0->O 1 0.551 0.801 clockkernel/Mmux_N61 (N_5_OBUF)
OBUF:I->O 5.644 N_5_OBUF (N<5>)
----------------------------------------
Total 14.394ns (8.928ns logic, 5.466ns route)
(62.0% logic, 38.0% route)
=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clockkernel/hclkbuf'
Total number of paths / destination ports: 62 / 8
-------------------------------------------------------------------------
Offset: 14.155ns (Levels of Logic = 6)
Source: clockkernel/hour_1_0 (FF)
Destination: N<5> (PAD)
Source Clock: clockkernel/hclkbuf rising
Data Path: clockkernel/hour_1_0 to N<5>
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDPE:C->Q 6 0.720 1.198 clockkernel/hour_1_0 (clockkernel/hour_1_0)
LUT3:I1->O 1 0.551 0.827 clockkernel/scan<9>1 (clockkernel/scan<9>1)
LUT4:I3->O 1 0.551 0.000 clockkernel/Mmux_dispdata_5_f5_F (N442)
MUXF5:I0->O 1 0.360 0.996 clockkernel/Mmux_dispdata_5_f5 (clockkernel/Mmux_dispdata_5_f5)
LUT3:I1->O 7 0.551 1.405 clockkernel/screen_or000011 (clockkernel/dispdata<0>)
LUT4:I0->O 1 0.551 0.801 clockkernel/Mmux_N61 (N_5_OBUF)
OBUF:I->O 5.644 N_5_OBUF (N<5>)
----------------------------------------
Total 14.155ns (8.928ns logic, 5.227ns route)
(63.1% logic, 36.9% route)
=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clockkernel/sclkbuf'
Total number of paths / destination ports: 62 / 8
-------------------------------------------------------------------------
Offset: 14.318ns (Levels of Logic = 6)
Source: clockkernel/sec_1_0 (FF)
Destination: N<5> (PAD)
Source Clock: clockkernel/sclkbuf rising
Data Path: clockkernel/sec_1_0 to N<5>
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDCE:C->Q 9 0.720 1.319 clockkernel/sec_1_0 (clockkernel/sec_1_0)
LUT3:I1->O 1 0.551 0.869 clockkernel/scan<9>11 (clockkernel/scan<9>2)
LUT4:I2->O 1 0.551 0.000 clockkernel/Mmux_dispdata_5_f5_G (N443)
MUXF5:I1->O 1 0.360 0.996 clockkernel/Mmux_dispdata_5_f5 (clockkernel/Mmux_dispdata_5_f5)
LUT3:I1->O 7 0.551 1.405 clockkernel/screen_or000011 (clockkernel/dispdata<0>)
LUT4:I0->O 1 0.551 0.801 clockkernel/Mmux_N61 (N_5_OBUF)
OBUF:I->O 5.644 N_5_OBUF (N<5>)
----------------------------------------
Total 14.318ns (8.928ns logic, 5.390ns route)
(62.4% logic, 37.6% route)
=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clockkernel/moncbuf'
Total number of paths / destination ports: 62 / 8
-------------------------------------------------------------------------
Offset: 13.072ns (Levels of Logic = 6)
Source: clockkernel/month_1_0 (FF)
Destination: N<5> (PAD)
Source Clock: clockkernel/moncbuf rising
Data Path: clockkernel/month_1_0 to N<5>
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDCE:C->Q 8 0.720 1.278 clockkernel/month_1_0 (clockkernel/month_1_0)
LUT3:I1->O 1 0.551 0.000 clockkernel/Mmux_dispdata_10 (clockkernel/N71)
MUXF5:I0->O 1 0.360 0.000 clockkernel/Mmux_dispdata_8_f5 (clockkernel/Mmux_dispdata_8_f5)
MUXF6:I0->O 1 0.342 0.869 clockkernel/Mmux_dispdata_6_f6 (clockkernel/Mmux_dispdata_6_f6)
LUT3:I2->O 7 0.551 1.405 clockkernel/screen_or000011 (clockkernel/dispdata<0>)
LUT4:I0->O 1 0.551 0.801 clockkernel/Mmux_N61 (N_5_OBUF)
OBUF:I->O 5.644 N_5_OBUF (N<5>)
----------------------------------------
Total 13.072ns (8.719ns logic, 4.353ns route)
(66.7% logic, 33.3% route)
=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clockkernel/daycbuf'
Total number of paths / destination ports: 62 / 8
-------------------------------------------------------------------------
Offset: 12.992ns (Levels of Logic = 6)
Source: clockkernel/day_1_0 (FF)
Destination: N<5> (PAD)
Source Clock: clockkernel/daycbuf rising
Data Path: clockkernel/day_1_0 to N<5>
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDCE:C->Q 6 0.720 1.198 clockkernel/day_1_0 (clockkernel/day_1_0)
LUT3:I1->O 1 0.551 0.000 clockkernel/Mmux_dispdata_91 (clockkernel/N61)
MUXF5:I1->O 1 0.360 0.000 clockkernel/Mmux_dispdata_8_f5 (clockkernel/Mmux_dispdata_8_f5)
MUXF6:I0->O 1 0.342 0.869 clockkernel/Mmux_dispdata_6_f6 (clockkernel/Mmux_dispdata_6_f6)
LUT3:I2->O 7 0.551 1.405 clockkernel/screen_or000011 (clockkernel/dispdata<0>)
LUT4:I0->O 1 0.551 0.801 clockkernel/Mmux_N61 (N_5_OBUF)
OBUF:I->O 5.644 N_5_OBUF (N<5>)
----------------------------------------
Total 12.992ns (8.719ns logic, 4.273ns route)
(67.1% logic, 32.9% route)
=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clockkernel/y4buf'
Total number of paths / destination ports: 31 / 8
-------------------------------------------------------------------------
Offset: 12.923ns (Levels of Logic = 6)
Source: clockkernel/year_3_1 (FF)
Destination: N<3> (PAD)
Source Clock: clockkernel/y4buf rising
Data Path: clockkernel/year_3_1 to N<3>
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDPE:C->Q 4 0.720 1.112 clockkernel/year_3_1 (clockkernel/year_3_1)
LUT3:I1->O 1 0.551 0.000 clockkernel/Mmux_dispdata_92 (clockkernel/N111)
MUXF5:I0->O 1 0.360 0.000 clockkernel/Mmux_dispdata_7_f5_0 (clockkernel/Mmux_dispdata_7_f51)
MUXF6:I1->O 1 0.342 0.869 clockkernel/Mmux_dispdata_6_f6_0 (clockkernel/Mmux_dispdata_6_f61)
LUT3:I2->O 8 0.551 1.422 clockkernel/screen_or0000111 (clockkernel/dispdata<1>)
LUT4:I0->O 1 0.551 0.801 clockkernel/Mmux_N31 (N_2_OBUF)
OBUF:I->O 5.644 N_2_OBUF (N<2>)
----------------------------------------
Total 12.923ns (8.719ns logic, 4.204ns route)
(67.5% logic, 32.5% route)
=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clockkernel/y3buf'
Total number of paths / destination ports: 31 / 8
-------------------------------------------------------------------------
Offset: 12.865ns (Levels of Logic = 6)
Source: clockkernel/year_2_0 (FF)
Destination: N<5> (PAD)
Source Clock: clockkernel/y3buf rising
Data Path: clockkernel/year_2_0 to N<5>
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDCE:C->Q 6 0.720 1.071 clockkernel/year_2_0 (clockkernel/year_2_0)
LUT3:I2->O 1 0.551 0.000 clockkernel/Mmux_dispdata_9 (clockkernel/N51)
MUXF5:I0->O 1 0.360 0.000 clockkernel/Mmux_dispdata_7_f5 (clockkernel/Mmux_dispdata_7_f5)
MUXF6:I1->O 1 0.342 0.869 clockkernel/Mmux_dispdata_6_f6 (clockkernel/Mmux_dispdata_6_f6)
LUT3:I2->O 7 0.551 1.405 clockkernel/screen_or000011 (clockkernel/dispdata<0>)
LUT4:I0->O 1 0.551 0.801 clockkernel/Mmux_N61 (N_5_OBUF)
OBUF:I->O 5.644 N_5_OBUF (N<5>)
----------------------------------------
Total 12.865ns (8.719ns logic, 4.146ns route)
(67.8% logic, 32.2% route)
=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clockkernel/y2buf'
Total number of paths / destination ports: 31 / 8
-------------------------------------------------------------------------
Offset: 13.055ns (Levels of Logic = 6)
Source: clockkernel/year_1_0 (FF)
Destination: N<5> (PAD)
Source Clock: clockkernel/y2buf rising
Data Path: clockkernel/year_1_0 to N<5>
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDCE:C->Q 7 0.720 1.261 clockkernel/year_1_0 (clockkernel/year_1_0)
LUT3:I1->O 1 0.551 0.000 clockkernel/Mmux_dispdata_8 (clockkernel/N41)
MUXF5:I1->O 1 0.360 0.000 clockkernel/Mmux_dispdata_7_f5 (clockkernel/Mmux_dispdata_7_f5)
MUXF6:I1->O 1 0.342 0.869 clockkernel/Mmux_dispdata_6_f6 (clockkernel/Mmux_dispdata_6_f6)
LUT3:I2->O 7 0.551 1.405 clockkernel/screen_or000011 (clockkernel/dispdata<0>)
LUT4:I0->O 1 0.551 0.801 clockkernel/Mmux_N61 (N_5_OBUF)
OBUF:I->O 5.644 N_5_OBUF (N<5>)
----------------------------------------
Total 13.055ns (8.719ns logic, 4.336ns route)
(66.8% logic, 33.2% route)
=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clockkernel/y1buf'
Total number of paths / destination ports: 31 / 8
-------------------------------------------------------------------------
Offset: 12.928ns (Levels of Logic = 6)
Source: clockkernel/year_0_0 (FF)
Destination: N<5> (PAD)
Source Clock: clockkernel/y1buf rising
Data Path: clockkernel/year_0_0 to N<5>
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDPE:C->Q 7 0.720 1.134 clockkernel/year_0_0 (clockkernel/year_0_0)
LUT3:I2->O 1 0.551 0.000 clockkernel/Mmux_dispdata_8 (clockkernel/N41)
MUXF5:I1->O 1 0.360 0.000 clockkernel/Mmux_dispdata_7_f5 (clockkernel/Mmux_dispdata_7_f5)
MUXF6:I1->O 1 0.342 0.869 clockkernel/Mmux_dispdata_6_f6 (clockkernel/Mmux_dispdata_6_f6)
LUT3:I2->O 7 0.551 1.405 clockkernel/screen_or000011 (clockkernel/dispdata<0>)
LUT4:I0->O 1 0.551 0.801 clockkernel/Mmux_N61 (N_5_OBUF)
OBUF:I->O 5.644 N_5_OBUF (N<5>)
----------------------------------------
Total 12.928ns (8.719ns logic, 4.209ns route)
(67.4% logic, 32.6% route)
=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'shake/noshakeb3'
Total number of paths / destination ports: 22 / 4
-------------------------------------------------------------------------
Offset: 14.232ns (Levels of Logic = 5)
Source: clockkernel/state_FFd1 (FF)
Destination: P<3> (PAD)
Source Clock: shake/noshakeb3 falling
Data Path: clockkernel/state_FFd1 to P<3>
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDC_1:C->Q 23 0.720 1.896 clockkernel/state_FFd1 (clockkernel/state_FFd1)
LUT3:I1->O 3 0.551 1.102 clockkernel/state_FFd2-In21 (clockkernel/state_FFd1-In)
LUT4:I1->O 1 0.551 0.996 clockkernel/P<3>20 (clockkernel/P<3>_map11)
LUT4:I1->O 1 0.551 0.869 clockkernel/P<3>41_SW0 (N402)
LUT3:I2->O 1 0.551 0.801 clockkernel/P<3>41 (P_3_OBUF)
OBUF:I->O 5.644 P_3_OBUF (P<3>)
----------------------------------------
Total 14.232ns (8.568ns logic, 5.664ns route)
(60.2% logic, 39.8% route)
=========================================================================
CPU : 10.58 / 11.22 s | Elapsed : 11.00 / 11.00 s
-->
Total memory usage is 146808 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 6 ( 0 filtered)
Number of infos : 1 ( 0 filtered)