www.pudn.com > eternityclock.rar > clocktop.drc
WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net clockkernel_mclkbuf is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net clockkernel_sclkbuf is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net clockkernel_moncbuf is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net clockkernel_daycbuf is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net clockkernel_y1buf is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net clockkernel_y2buf is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net clockkernel_y3buf is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net clockkernel_y4buf is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net clockkernel_hclkbuf is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. DRC detected 0 errors and 9 warnings.