www.pudn.com > eternityclock.rar > clocktop.bld

Release 9.2i ngdbuild J.36
Copyright (c) 1995-2007 Xilinx, Inc.  All rights reserved.

Command Line: E:\Xilinx92i\bin\nt\ngdbuild.exe -ise 
F:/FPGA/vhdl_course/samples/eternityclock/eternityclock.ise -intstyle ise -dd 
_ngo -nt timestamp -uc clocktop.ucf -p xc3s400-pq208-4 clocktop.ngc clocktop.ngd

Reading NGO file "F:/FPGA/vhdl_course/samples/eternityclock/clocktop.ngc" ...

Applying constraints in "clocktop.ucf" to the design...

Checking timing specifications ...
Checking Partitions ...
Checking expanded design ...

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Total memory usage is 71744 kilobytes

Writing NGD file "clocktop.ngd" ...

Writing NGDBUILD log file "clocktop.bld"...