www.pudn.com > eternityclock.rar > clockcore.twr
--------------------------------------------------------------------------------
Release 6.1i Trace G.23
Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved.
D:/Xilinx/bin/nt/trce.exe -intstyle ise -e 3 -l 3 -xml clockcore clockcore.ncd
-o clockcore.twr clockcore.pcf
Design file: clockcore.ncd
Physical constraint file: clockcore.pcf
Device,speed: xc3s400,-4 (PREVIEW 1.26 2003-06-19)
Report level: error report
Environment Variable Effect
-------------------- ------
NONE No environment variables were set
--------------------------------------------------------------------------------
INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
option. All paths that are not constrained will be reported in the
unconstrained paths section(s) of the report.
Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)
Clock b2 to Pad
------------+------------+------------------+--------+
| clk (edge) | | Clock |
Destination | to PAD |Internal Clock(s) | Phase |
------------+------------+------------------+--------+
N<0> | 16.885(R)|moncbuf | 0.000|
| 16.934(R)|daycbuf | 0.000|
| 16.460(R)|y2buf | 0.000|
| 17.661(R)|y1buf | 0.000|
| 17.821(R)|y4buf | 0.000|
| 17.733(R)|y3buf | 0.000|
| 17.273(R)|sclkbuf | 0.000|
| 17.052(R)|hclkbuf | 0.000|
| 17.700(R)|mclkbuf | 0.000|
N<1> | 17.385(R)|moncbuf | 0.000|
| 17.672(R)|daycbuf | 0.000|
| 17.118(R)|y2buf | 0.000|
| 18.399(R)|y1buf | 0.000|
| 18.559(R)|y4buf | 0.000|
| 18.436(R)|y3buf | 0.000|
| 17.508(R)|sclkbuf | 0.000|
| 17.772(R)|hclkbuf | 0.000|
| 18.433(R)|mclkbuf | 0.000|
N<2> | 17.195(R)|moncbuf | 0.000|
| 17.049(R)|daycbuf | 0.000|
| 16.756(R)|y2buf | 0.000|
| 17.776(R)|y1buf | 0.000|
| 17.936(R)|y4buf | 0.000|
| 18.029(R)|y3buf | 0.000|
| 17.569(R)|sclkbuf | 0.000|
| 17.348(R)|hclkbuf | 0.000|
| 17.813(R)|mclkbuf | 0.000|
N<3> | 17.122(R)|moncbuf | 0.000|
| 16.973(R)|daycbuf | 0.000|
| 16.697(R)|y2buf | 0.000|
| 17.700(R)|y1buf | 0.000|
| 17.860(R)|y4buf | 0.000|
| 17.970(R)|y3buf | 0.000|
| 17.510(R)|sclkbuf | 0.000|
| 17.289(R)|hclkbuf | 0.000|
| 17.754(R)|mclkbuf | 0.000|
N<4> | 17.360(R)|moncbuf | 0.000|
| 17.641(R)|daycbuf | 0.000|
| 17.087(R)|y2buf | 0.000|
| 18.368(R)|y1buf | 0.000|
| 18.557(R)|y4buf | 0.000|
| 18.445(R)|y3buf | 0.000|
| 17.482(R)|sclkbuf | 0.000|
| 17.781(R)|hclkbuf | 0.000|
| 18.442(R)|mclkbuf | 0.000|
N<5> | 17.330(R)|moncbuf | 0.000|
| 17.356(R)|daycbuf | 0.000|
| 16.905(R)|y2buf | 0.000|
| 18.083(R)|y1buf | 0.000|
| 18.277(R)|y4buf | 0.000|
| 18.178(R)|y3buf | 0.000|
| 17.718(R)|sclkbuf | 0.000|
| 17.501(R)|hclkbuf | 0.000|
| 18.162(R)|mclkbuf | 0.000|
N<6> | 17.727(R)|moncbuf | 0.000|
| 17.836(R)|daycbuf | 0.000|
| 17.282(R)|y2buf | 0.000|
| 18.563(R)|y1buf | 0.000|
| 18.723(R)|y4buf | 0.000|
| 18.578(R)|y3buf | 0.000|
| 17.819(R)|sclkbuf | 0.000|
| 17.914(R)|hclkbuf | 0.000|
| 18.575(R)|mclkbuf | 0.000|
N<7> | 17.476(R)|sclkbuf | 0.000|
| 17.739(R)|hclkbuf | 0.000|
| 18.400(R)|mclkbuf | 0.000|
| 17.318(R)|moncbuf | 0.000|
| 17.549(R)|daycbuf | 0.000|
| 18.403(R)|y3buf | 0.000|
| 18.515(R)|y4buf | 0.000|
| 18.203(R)|y1buf | 0.000|
| 16.922(R)|y2buf | 0.000|
------------+------------+------------------+--------+
Clock b3 to Pad
------------+------------+------------------+--------+
| clk (edge) | | Clock |
Destination | to PAD |Internal Clock(s) | Phase |
------------+------------+------------------+--------+
N<0> | 18.285(F)|b3_BUFGP | 0.000|
N<1> | 19.018(F)|b3_BUFGP | 0.000|
N<2> | 18.441(F)|b3_BUFGP | 0.000|
N<3> | 18.382(F)|b3_BUFGP | 0.000|
N<4> | 19.027(F)|b3_BUFGP | 0.000|
N<5> | 18.747(F)|b3_BUFGP | 0.000|
N<6> | 19.160(F)|b3_BUFGP | 0.000|
N<7> | 18.985(F)|b3_BUFGP | 0.000|
P<0> | 14.487(F)|b3_BUFGP | 0.000|
P<1> | 15.797(F)|b3_BUFGP | 0.000|
P<2> | 15.935(F)|b3_BUFGP | 0.000|
P<3> | 16.357(F)|b3_BUFGP | 0.000|
------------+------------+------------------+--------+
Clock b4 to Pad
------------+------------+------------------+--------+
| clk (edge) | | Clock |
Destination | to PAD |Internal Clock(s) | Phase |
------------+------------+------------------+--------+
N<0> | 16.716(F)|b4_BUFGP | 0.000|
N<1> | 17.170(F)|b4_BUFGP | 0.000|
N<2> | 17.012(F)|b4_BUFGP | 0.000|
N<3> | 16.953(F)|b4_BUFGP | 0.000|
N<4> | 17.139(F)|b4_BUFGP | 0.000|
N<5> | 17.161(F)|b4_BUFGP | 0.000|
N<6> | 17.334(F)|b4_BUFGP | 0.000|
N<7> | 17.060(F)|b4_BUFGP | 0.000|
P<1> | 14.368(F)|b4_BUFGP | 0.000|
P<2> | 14.490(F)|b4_BUFGP | 0.000|
P<3> | 14.432(F)|b4_BUFGP | 0.000|
------------+------------+------------------+--------+
Clock clk to Pad
------------+------------+------------------+--------+
| clk (edge) | | Clock |
Destination | to PAD |Internal Clock(s) | Phase |
------------+------------+------------------+--------+
N<0> | 15.026(R)|clk_BUFGP | 0.000|
N<1> | 15.472(R)|clk_BUFGP | 0.000|
N<2> | 15.322(R)|clk_BUFGP | 0.000|
N<3> | 15.263(R)|clk_BUFGP | 0.000|
N<4> | 15.481(R)|clk_BUFGP | 0.000|
N<5> | 15.471(R)|clk_BUFGP | 0.000|
N<6> | 15.614(R)|clk_BUFGP | 0.000|
N<7> | 15.439(R)|clk_BUFGP | 0.000|
P<0> | 11.751(R)|clk_BUFGP | 0.000|
P<1> | 11.742(R)|clk_BUFGP | 0.000|
P<2> | 12.228(R)|clk_BUFGP | 0.000|
P<3> | 12.490(R)|clk_BUFGP | 0.000|
------------+------------+------------------+--------+
Clock to Setup on destination clock b2
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
b2 | 9.696| | | |
---------------+---------+---------+---------+---------+
Clock to Setup on destination clock b3
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
b3 | | | | 3.383|
b4 | | | | 2.599|
---------------+---------+---------+---------+---------+
Clock to Setup on destination clock b4
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
b4 | | | | 2.211|
---------------+---------+---------+---------+---------+
Clock to Setup on destination clock clk
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk | 10.021| | | |
---------------+---------+---------+---------+---------+
Analysis completed Tue Jul 31 21:57:07 2007
--------------------------------------------------------------------------------
Peak Memory Usage: 61 MB