www.pudn.com > eternityclock.rar > clockcore.drc

WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net daycbuf is sourced by 
   a combinatorial pin. This is not good design practice. Use the CE pin to 
   control the loading of data into the flip-flop.
WARNING:DesignRules:367 - Netcheck: Loadless. Net day_0__n0001<3> has no load.
WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net y2buf is sourced by a 
   combinatorial pin. This is not good design practice. Use the CE pin to 
   control the loading of data into the flip-flop.
WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net y3buf is sourced by a 
   combinatorial pin. This is not good design practice. Use the CE pin to 
   control the loading of data into the flip-flop.
WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net y4buf is sourced by a 
   combinatorial pin. This is not good design practice. Use the CE pin to 
   control the loading of data into the flip-flop.
WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net hclkbuf is sourced by 
   a combinatorial pin. This is not good design practice. Use the CE pin to 
   control the loading of data into the flip-flop.
WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net _n0144 is sourced by 
   a combinatorial pin. This is not good design practice. Use the CE pin to 
   control the loading of data into the flip-flop.
WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net sclkbuf is sourced by 
   a combinatorial pin. This is not good design practice. Use the CE pin to 
   control the loading of data into the flip-flop.
WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net mclkbuf is sourced by 
   a combinatorial pin. This is not good design practice. Use the CE pin to 
   control the loading of data into the flip-flop.
WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net moncbuf is sourced by 
   a combinatorial pin. This is not good design practice. Use the CE pin to 
   control the loading of data into the flip-flop.
WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net y1buf is sourced by a 
   combinatorial pin. This is not good design practice. Use the CE pin to 
   control the loading of data into the flip-flop.
DRC detected 0 errors and 11 warnings.