www.pudn.com > eternityclock.rar > clockcore.bgn

Release 6.1i - Bitgen G.23
Copyright (c) 1995-2003 Xilinx, Inc.  All rights reserved.

Loading device database for application Bitgen from file "clockcore.ncd".
   "clockcore" is an NCD, version 2.38, device xc3s400, package pq208, speed -4
Loading device for application Bitgen from file '3s400.nph' in environment 
D:/Xilinx.
Opened constraints file clockcore.pcf.

Tue Jul 31 21:57:10 2007

D:/Xilinx/bin/nt/bitgen.exe -intstyle ise -g DebugBitstream:No -w -g Binary:no -g CRC:Enable -g ConfigRate:6 -g CclkPin:PullUp -g M0Pin:PullUp -g M1Pin:PullUp -g M2Pin:PullUp -g ProgPin:PullUp -g DonePin:PullUp -g TckPin:PullUp -g TdiPin:PullUp -g TdoPin:PullUp -g TmsPin:PullUp -g UnusedPin:PullDown -g UserID:0xFFFFFFFF -g DCMShutDown:Disable -g StartUpClk:CClk -g DONE_cycle:4 -g GTS_cycle:5 -g GWE_cycle:6 -g LCK_cycle:NoWait -g Match_cycle:NoWait -g Security:None -g DonePipe:No -g DriveDone:No clockcore.ncd 
 
Summary of Bitgen Options: 
+----------------------+----------------------+ 
| Option Name          | Current Setting      | 
+----------------------+----------------------+ 
| Compress             | (Not Specified)*     | 
+----------------------+----------------------+ 
| Readback             | (Not Specified)*     | 
+----------------------+----------------------+ 
| CRC                  | Enable**             | 
+----------------------+----------------------+ 
| DebugBitstream       | No**                 | 
+----------------------+----------------------+ 
| ConfigRate           | 6**                  | 
+----------------------+----------------------+ 
| StartupClk           | Cclk**               | 
+----------------------+----------------------+ 
| DCMShutdown          | Disable**            | 
+----------------------+----------------------+ 
| DCIUpdateMode        | AsRequired*          | 
+----------------------+----------------------+ 
| CclkPin              | Pullup**             | 
+----------------------+----------------------+ 
| DonePin              | Pullup**             | 
+----------------------+----------------------+ 
| HswapenPin           | Pullup*              | 
+----------------------+----------------------+ 
| M0Pin                | Pullup**             | 
+----------------------+----------------------+ 
| M1Pin                | Pullup**             | 
+----------------------+----------------------+ 
| M2Pin                | Pullup**             | 
+----------------------+----------------------+ 
| ProgPin              | Pullup**             | 
+----------------------+----------------------+ 
| TckPin               | Pullup**             | 
+----------------------+----------------------+ 
| TdiPin               | Pullup**             | 
+----------------------+----------------------+ 
| TdoPin               | Pullup**             | 
+----------------------+----------------------+ 
| TmsPin               | Pullup**             | 
+----------------------+----------------------+ 
| UnusedPin            | Pulldown**           | 
+----------------------+----------------------+ 
| GWE_cycle            | 6**                  | 
+----------------------+----------------------+ 
| GTS_cycle            | 5**                  | 
+----------------------+----------------------+ 
| LCK_cycle            | NoWait**             | 
+----------------------+----------------------+ 
| Match_cycle          | NoWait               | 
+----------------------+----------------------+ 
| DONE_cycle           | 4**                  | 
+----------------------+----------------------+ 
| Persist              | No*                  | 
+----------------------+----------------------+ 
| DriveDone            | No**                 | 
+----------------------+----------------------+ 
| DonePipe             | No**                 | 
+----------------------+----------------------+ 
| Security             | None**               | 
+----------------------+----------------------+ 
| UserID               | 0xFFFFFFFF**         | 
+----------------------+----------------------+ 
| ActivateGclk         | No*                  | 
+----------------------+----------------------+ 
| ActiveReconfig       | No*                  | 
+----------------------+----------------------+ 
| PartialMask0         | (Not Specified)*     | 
+----------------------+----------------------+ 
| PartialMask1         | (Not Specified)*     | 
+----------------------+----------------------+ 
| PartialMask2         | (Not Specified)*     | 
+----------------------+----------------------+ 
| PartialGclk          | (Not Specified)*     | 
+----------------------+----------------------+ 
| PartialLeft          | (Not Specified)*     | 
+----------------------+----------------------+ 
| PartialRight         | (Not Specified)*     | 
+----------------------+----------------------+ 
| IEEE1532             | No*                  | 
+----------------------+----------------------+ 
| Binary               | No**                 | 
+----------------------+----------------------+ 
 *  Default setting. 
 ** The specified setting matches the default setting. 
 
Running DRC.
WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net daycbuf is sourced by 
   a combinatorial pin. This is not good design practice. Use the CE pin to 
   control the loading of data into the flip-flop.
WARNING:DesignRules:367 - Netcheck: Loadless. Net day_0__n0001<3> has no load.
WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net y2buf is sourced by a 
   combinatorial pin. This is not good design practice. Use the CE pin to 
   control the loading of data into the flip-flop.
WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net y3buf is sourced by a 
   combinatorial pin. This is not good design practice. Use the CE pin to 
   control the loading of data into the flip-flop.
WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net y4buf is sourced by a 
   combinatorial pin. This is not good design practice. Use the CE pin to 
   control the loading of data into the flip-flop.
WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net hclkbuf is sourced by 
   a combinatorial pin. This is not good design practice. Use the CE pin to 
   control the loading of data into the flip-flop.
WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net _n0144 is sourced by 
   a combinatorial pin. This is not good design practice. Use the CE pin to 
   control the loading of data into the flip-flop.
WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net sclkbuf is sourced by 
   a combinatorial pin. This is not good design practice. Use the CE pin to 
   control the loading of data into the flip-flop.
WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net mclkbuf is sourced by 
   a combinatorial pin. This is not good design practice. Use the CE pin to 
   control the loading of data into the flip-flop.
WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net moncbuf is sourced by 
   a combinatorial pin. This is not good design practice. Use the CE pin to 
   control the loading of data into the flip-flop.
WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net y1buf is sourced by a 
   combinatorial pin. This is not good design practice. Use the CE pin to 
   control the loading of data into the flip-flop.
DRC detected 0 errors and 11 warnings.
Creating bit map...
Saving bit stream in "clockcore.bit".
Bitstream generation is complete.