www.pudn.com > Time.rar > Time.hier_info

|Time 
KEY[0] => ~NO_FANOUT~ 
KEY[1] => KEY[1]~2.IN1 
KEY[2] => KEY[2]~1.IN1 
KEY[3] => KEY[3]~0.IN1 
SW[0] => ~NO_FANOUT~ 
SW[1] => ~NO_FANOUT~ 
SW[2] => ~NO_FANOUT~ 
SW[3] => ~NO_FANOUT~ 
SW[4] => ~NO_FANOUT~ 
SW[5] => ~NO_FANOUT~ 
SW[6] => ~NO_FANOUT~ 
SW[7] => ~NO_FANOUT~ 
SW[8] => ~NO_FANOUT~ 
SW[9] => ~NO_FANOUT~ 
SW[10] => ~NO_FANOUT~ 
SW[11] => ~NO_FANOUT~ 
SW[12] => ~NO_FANOUT~ 
SW[13] => ~NO_FANOUT~ 
SW[14] => ~NO_FANOUT~ 
SW[15] => ~NO_FANOUT~ 
SW[16] => ~NO_FANOUT~ 
SW[17] => SW[17]~0.IN9 
CLOCK_50 => CLOCK_50~0.IN3 
LEDG[0] <=  
LEDG[1] <=  
LEDG[2] <=  
LEDG[3] <=  
LEDG[4] <=  
LEDG[5] <=  
LEDG[6] <=  
LEDG[7] <=  
LEDG[8] <=  
HEX7[0] <= DecDis:HC1.port3 
HEX7[1] <= DecDis:HC1.port3 
HEX7[2] <= DecDis:HC1.port3 
HEX7[3] <= DecDis:HC1.port3 
HEX7[4] <= DecDis:HC1.port3 
HEX7[5] <= DecDis:HC1.port3 
HEX7[6] <= DecDis:HC1.port3 
HEX6[0] <= DecDis:HC0.port3 
HEX6[1] <= DecDis:HC0.port3 
HEX6[2] <= DecDis:HC0.port3 
HEX6[3] <= DecDis:HC0.port3 
HEX6[4] <= DecDis:HC0.port3 
HEX6[5] <= DecDis:HC0.port3 
HEX6[6] <= DecDis:HC0.port3 
HEX3[0] <= DecDis:MC1.port3 
HEX3[1] <= DecDis:MC1.port3 
HEX3[2] <= DecDis:MC1.port3 
HEX3[3] <= DecDis:MC1.port3 
HEX3[4] <= DecDis:MC1.port3 
HEX3[5] <= DecDis:MC1.port3 
HEX3[6] <= DecDis:MC1.port3 
HEX2[0] <= DecDis:MC0.port3 
HEX2[1] <= DecDis:MC0.port3 
HEX2[2] <= DecDis:MC0.port3 
HEX2[3] <= DecDis:MC0.port3 
HEX2[4] <= DecDis:MC0.port3 
HEX2[5] <= DecDis:MC0.port3 
HEX2[6] <= DecDis:MC0.port3 
HEX1[0] <= DecDis:SC1.port3 
HEX1[1] <= DecDis:SC1.port3 
HEX1[2] <= DecDis:SC1.port3 
HEX1[3] <= DecDis:SC1.port3 
HEX1[4] <= DecDis:SC1.port3 
HEX1[5] <= DecDis:SC1.port3 
HEX1[6] <= DecDis:SC1.port3 
HEX0[0] <= DecDis:SC0.port3 
HEX0[1] <= DecDis:SC0.port3 
HEX0[2] <= DecDis:SC0.port3 
HEX0[3] <= DecDis:SC0.port3 
HEX0[4] <= DecDis:SC0.port3 
HEX0[5] <= DecDis:SC0.port3 
HEX0[6] <= DecDis:SC0.port3 
 
 
|Time|SecClkGen:SCG1 
clk => countc[25].CLK 
clk => countc[24].CLK 
clk => countc[23].CLK 
clk => countc[22].CLK 
clk => countc[21].CLK 
clk => countc[20].CLK 
clk => countc[19].CLK 
clk => countc[18].CLK 
clk => countc[17].CLK 
clk => countc[16].CLK 
clk => countc[15].CLK 
clk => countc[14].CLK 
clk => countc[13].CLK 
clk => countc[12].CLK 
clk => countc[11].CLK 
clk => countc[10].CLK 
clk => countc[9].CLK 
clk => countc[8].CLK 
clk => countc[7].CLK 
clk => countc[6].CLK 
clk => countc[5].CLK 
clk => countc[4].CLK 
clk => countc[3].CLK 
clk => countc[2].CLK 
clk => countc[1].CLK 
clk => countc[0].CLK 
clk => counts[5].CLK 
clk => counts[4].CLK 
clk => counts[3].CLK 
clk => counts[2].CLK 
clk => counts[1].CLK 
clk => counts[0].CLK 
rst => countc[25].ACLR 
rst => countc[24].ACLR 
rst => countc[23].ACLR 
rst => countc[22].ACLR 
rst => countc[21].ACLR 
rst => countc[20].ACLR 
rst => countc[19].ACLR 
rst => countc[18].ACLR 
rst => countc[17].ACLR 
rst => countc[16].ACLR 
rst => countc[15].ACLR 
rst => countc[14].ACLR 
rst => countc[13].ACLR 
rst => countc[12].ACLR 
rst => countc[11].ACLR 
rst => countc[10].ACLR 
rst => countc[9].ACLR 
rst => countc[8].ACLR 
rst => countc[7].ACLR 
rst => countc[6].ACLR 
rst => countc[5].ACLR 
rst => countc[4].ACLR 
rst => countc[3].ACLR 
rst => countc[2].ACLR 
rst => countc[1].ACLR 
rst => countc[0].ACLR 
rst => counts[0].ENA 
rst => counts[5].ENA 
rst => counts[4].ENA 
rst => counts[3].ENA 
rst => counts[2].ENA 
rst => counts[1].ENA 
plus => ~NO_FANOUT~ 
Second[0] <= Mod0.DB_MAX_OUTPUT_PORT_TYPE 
Second[1] <= Mod0.DB_MAX_OUTPUT_PORT_TYPE 
Second[2] <= Mod0.DB_MAX_OUTPUT_PORT_TYPE 
Second[3] <= Mod0.DB_MAX_OUTPUT_PORT_TYPE 
Second[4] <= Div0.DB_MAX_OUTPUT_PORT_TYPE 
Second[5] <= Div0.DB_MAX_OUTPUT_PORT_TYPE 
Second[6] <= Div0.DB_MAX_OUTPUT_PORT_TYPE 
Second[7] <= Div0.DB_MAX_OUTPUT_PORT_TYPE 
SecClk <= countc[24].DB_MAX_OUTPUT_PORT_TYPE 
 
 
|Time|DecDis:SC1 
DecVal[0] => Decoder0.IN3 
DecVal[1] => Decoder0.IN2 
DecVal[2] => Decoder0.IN1 
DecVal[3] => Decoder0.IN0 
clc => HexVal[6]~reg0.CLK 
clc => HexVal[5]~reg0.CLK 
clc => HexVal[4]~reg0.CLK 
clc => HexVal[3]~reg0.CLK 
clc => HexVal[2]~reg0.CLK 
clc => HexVal[1]~reg0.CLK 
clc => HexVal[0]~reg0.CLK 
rst => HexVal[6]~reg0.PRESET 
rst => HexVal[5]~reg0.PRESET 
rst => HexVal[4]~reg0.PRESET 
rst => HexVal[3]~reg0.PRESET 
rst => HexVal[2]~reg0.PRESET 
rst => HexVal[1]~reg0.PRESET 
rst => HexVal[0]~reg0.PRESET 
HexVal[0] <= HexVal[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE 
HexVal[1] <= HexVal[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE 
HexVal[2] <= HexVal[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE 
HexVal[3] <= HexVal[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE 
HexVal[4] <= HexVal[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE 
HexVal[5] <= HexVal[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE 
HexVal[6] <= HexVal[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE 
 
 
|Time|DecDis:SC0 
DecVal[0] => Decoder0.IN3 
DecVal[1] => Decoder0.IN2 
DecVal[2] => Decoder0.IN1 
DecVal[3] => Decoder0.IN0 
clc => HexVal[6]~reg0.CLK 
clc => HexVal[5]~reg0.CLK 
clc => HexVal[4]~reg0.CLK 
clc => HexVal[3]~reg0.CLK 
clc => HexVal[2]~reg0.CLK 
clc => HexVal[1]~reg0.CLK 
clc => HexVal[0]~reg0.CLK 
rst => HexVal[6]~reg0.PRESET 
rst => HexVal[5]~reg0.PRESET 
rst => HexVal[4]~reg0.PRESET 
rst => HexVal[3]~reg0.PRESET 
rst => HexVal[2]~reg0.PRESET 
rst => HexVal[1]~reg0.PRESET 
rst => HexVal[0]~reg0.PRESET 
HexVal[0] <= HexVal[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE 
HexVal[1] <= HexVal[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE 
HexVal[2] <= HexVal[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE 
HexVal[3] <= HexVal[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE 
HexVal[4] <= HexVal[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE 
HexVal[5] <= HexVal[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE 
HexVal[6] <= HexVal[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE 
 
 
|Time|MinClkGen:MCG1 
clk => countc[31].CLK 
clk => countc[30].CLK 
clk => countc[29].CLK 
clk => countc[28].CLK 
clk => countc[27].CLK 
clk => countc[26].CLK 
clk => countc[25].CLK 
clk => countc[24].CLK 
clk => countc[23].CLK 
clk => countc[22].CLK 
clk => countc[21].CLK 
clk => countc[20].CLK 
clk => countc[19].CLK 
clk => countc[18].CLK 
clk => countc[17].CLK 
clk => countc[16].CLK 
clk => countc[15].CLK 
clk => countc[14].CLK 
clk => countc[13].CLK 
clk => countc[12].CLK 
clk => countc[11].CLK 
clk => countc[10].CLK 
clk => countc[9].CLK 
clk => countc[8].CLK 
clk => countc[7].CLK 
clk => countc[6].CLK 
clk => countc[5].CLK 
clk => countc[4].CLK 
clk => countc[3].CLK 
clk => countc[2].CLK 
clk => countc[1].CLK 
clk => countc[0].CLK 
clk => countm[5].CLK 
clk => countm[4].CLK 
clk => countm[3].CLK 
clk => countm[2].CLK 
clk => countm[1].CLK 
clk => countm[0].CLK 
rst => countc[31].ACLR 
rst => countc[30].ACLR 
rst => countc[29].ACLR 
rst => countc[28].ACLR 
rst => countc[27].ACLR 
rst => countc[26].ACLR 
rst => countc[25].ACLR 
rst => countc[24].ACLR 
rst => countc[23].ACLR 
rst => countc[22].ACLR 
rst => countc[21].ACLR 
rst => countc[20].ACLR 
rst => countc[19].ACLR 
rst => countc[18].ACLR 
rst => countc[17].ACLR 
rst => countc[16].ACLR 
rst => countc[15].ACLR 
rst => countc[14].ACLR 
rst => countc[13].ACLR 
rst => countc[12].ACLR 
rst => countc[11].ACLR 
rst => countc[10].ACLR 
rst => countc[9].ACLR 
rst => countc[8].ACLR 
rst => countc[7].ACLR 
rst => countc[6].ACLR 
rst => countc[5].ACLR 
rst => countc[4].ACLR 
rst => countc[3].ACLR 
rst => countc[2].ACLR 
rst => countc[1].ACLR 
rst => countc[0].ACLR 
rst => countm[0].ENA 
rst => countm[5].ENA 
rst => countm[4].ENA 
rst => countm[3].ENA 
rst => countm[2].ENA 
rst => countm[1].ENA 
plus => ~NO_FANOUT~ 
Minute[0] <= Mod0.DB_MAX_OUTPUT_PORT_TYPE 
Minute[1] <= Mod0.DB_MAX_OUTPUT_PORT_TYPE 
Minute[2] <= Mod0.DB_MAX_OUTPUT_PORT_TYPE 
Minute[3] <= Mod0.DB_MAX_OUTPUT_PORT_TYPE 
Minute[4] <= Div0.DB_MAX_OUTPUT_PORT_TYPE 
Minute[5] <= Div0.DB_MAX_OUTPUT_PORT_TYPE 
Minute[6] <= Div0.DB_MAX_OUTPUT_PORT_TYPE 
Minute[7] <= Div0.DB_MAX_OUTPUT_PORT_TYPE 
 
 
|Time|DecDis:MC1 
DecVal[0] => Decoder0.IN3 
DecVal[1] => Decoder0.IN2 
DecVal[2] => Decoder0.IN1 
DecVal[3] => Decoder0.IN0 
clc => HexVal[6]~reg0.CLK 
clc => HexVal[5]~reg0.CLK 
clc => HexVal[4]~reg0.CLK 
clc => HexVal[3]~reg0.CLK 
clc => HexVal[2]~reg0.CLK 
clc => HexVal[1]~reg0.CLK 
clc => HexVal[0]~reg0.CLK 
rst => HexVal[6]~reg0.PRESET 
rst => HexVal[5]~reg0.PRESET 
rst => HexVal[4]~reg0.PRESET 
rst => HexVal[3]~reg0.PRESET 
rst => HexVal[2]~reg0.PRESET 
rst => HexVal[1]~reg0.PRESET 
rst => HexVal[0]~reg0.PRESET 
HexVal[0] <= HexVal[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE 
HexVal[1] <= HexVal[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE 
HexVal[2] <= HexVal[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE 
HexVal[3] <= HexVal[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE 
HexVal[4] <= HexVal[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE 
HexVal[5] <= HexVal[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE 
HexVal[6] <= HexVal[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE 
 
 
|Time|DecDis:MC0 
DecVal[0] => Decoder0.IN3 
DecVal[1] => Decoder0.IN2 
DecVal[2] => Decoder0.IN1 
DecVal[3] => Decoder0.IN0 
clc => HexVal[6]~reg0.CLK 
clc => HexVal[5]~reg0.CLK 
clc => HexVal[4]~reg0.CLK 
clc => HexVal[3]~reg0.CLK 
clc => HexVal[2]~reg0.CLK 
clc => HexVal[1]~reg0.CLK 
clc => HexVal[0]~reg0.CLK 
rst => HexVal[6]~reg0.PRESET 
rst => HexVal[5]~reg0.PRESET 
rst => HexVal[4]~reg0.PRESET 
rst => HexVal[3]~reg0.PRESET 
rst => HexVal[2]~reg0.PRESET 
rst => HexVal[1]~reg0.PRESET 
rst => HexVal[0]~reg0.PRESET 
HexVal[0] <= HexVal[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE 
HexVal[1] <= HexVal[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE 
HexVal[2] <= HexVal[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE 
HexVal[3] <= HexVal[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE 
HexVal[4] <= HexVal[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE 
HexVal[5] <= HexVal[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE 
HexVal[6] <= HexVal[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE 
 
 
|Time|HouClkGen:HCG1 
clk => countc[43].CLK 
clk => countc[42].CLK 
clk => countc[41].CLK 
clk => countc[40].CLK 
clk => countc[39].CLK 
clk => countc[38].CLK 
clk => countc[37].CLK 
clk => countc[36].CLK 
clk => countc[35].CLK 
clk => countc[34].CLK 
clk => countc[33].CLK 
clk => countc[32].CLK 
clk => countc[31].CLK 
clk => countc[30].CLK 
clk => countc[29].CLK 
clk => countc[28].CLK 
clk => countc[27].CLK 
clk => countc[26].CLK 
clk => countc[25].CLK 
clk => countc[24].CLK 
clk => countc[23].CLK 
clk => countc[22].CLK 
clk => countc[21].CLK 
clk => countc[20].CLK 
clk => countc[19].CLK 
clk => countc[18].CLK 
clk => countc[17].CLK 
clk => countc[16].CLK 
clk => countc[15].CLK 
clk => countc[14].CLK 
clk => countc[13].CLK 
clk => countc[12].CLK 
clk => countc[11].CLK 
clk => countc[10].CLK 
clk => countc[9].CLK 
clk => countc[8].CLK 
clk => countc[7].CLK 
clk => countc[6].CLK 
clk => countc[5].CLK 
clk => countc[4].CLK 
clk => countc[3].CLK 
clk => countc[2].CLK 
clk => countc[1].CLK 
clk => countc[0].CLK 
clk => counth[4].CLK 
clk => counth[3].CLK 
clk => counth[2].CLK 
clk => counth[1].CLK 
clk => counth[0].CLK 
rst => countc[43].ACLR 
rst => countc[42].ACLR 
rst => countc[41].ACLR 
rst => countc[40].ACLR 
rst => countc[39].ACLR 
rst => countc[38].ACLR 
rst => countc[37].ACLR 
rst => countc[36].ACLR 
rst => countc[35].ACLR 
rst => countc[34].ACLR 
rst => countc[33].ACLR 
rst => countc[32].ACLR 
rst => countc[31].ACLR 
rst => countc[30].ACLR 
rst => countc[29].ACLR 
rst => countc[28].ACLR 
rst => countc[27].ACLR 
rst => countc[26].ACLR 
rst => countc[25].ACLR 
rst => countc[24].ACLR 
rst => countc[23].ACLR 
rst => countc[22].ACLR 
rst => countc[21].ACLR 
rst => countc[20].ACLR 
rst => countc[19].ACLR 
rst => countc[18].ACLR 
rst => countc[17].ACLR 
rst => countc[16].ACLR 
rst => countc[15].ACLR 
rst => countc[14].ACLR 
rst => countc[13].ACLR 
rst => countc[12].ACLR 
rst => countc[11].ACLR 
rst => countc[10].ACLR 
rst => countc[9].ACLR 
rst => countc[8].ACLR 
rst => countc[7].ACLR 
rst => countc[6].ACLR 
rst => countc[5].ACLR 
rst => countc[4].ACLR 
rst => countc[3].ACLR 
rst => countc[2].ACLR 
rst => countc[1].ACLR 
rst => countc[0].ACLR 
rst => counth[0].ENA 
rst => counth[4].ENA 
rst => counth[3].ENA 
rst => counth[2].ENA 
rst => counth[1].ENA 
plus => ~NO_FANOUT~ 
Hour[0] <= Mod0.DB_MAX_OUTPUT_PORT_TYPE 
Hour[1] <= Mod0.DB_MAX_OUTPUT_PORT_TYPE 
Hour[2] <= Mod0.DB_MAX_OUTPUT_PORT_TYPE 
Hour[3] <= Mod0.DB_MAX_OUTPUT_PORT_TYPE 
Hour[4] <= Div0.DB_MAX_OUTPUT_PORT_TYPE 
Hour[5] <= Div0.DB_MAX_OUTPUT_PORT_TYPE 
Hour[6] <= Div0.DB_MAX_OUTPUT_PORT_TYPE 
Hour[7] <= Div0.DB_MAX_OUTPUT_PORT_TYPE 
 
 
|Time|DecDis:HC1 
DecVal[0] => Decoder0.IN3 
DecVal[1] => Decoder0.IN2 
DecVal[2] => Decoder0.IN1 
DecVal[3] => Decoder0.IN0 
clc => HexVal[6]~reg0.CLK 
clc => HexVal[5]~reg0.CLK 
clc => HexVal[4]~reg0.CLK 
clc => HexVal[3]~reg0.CLK 
clc => HexVal[2]~reg0.CLK 
clc => HexVal[1]~reg0.CLK 
clc => HexVal[0]~reg0.CLK 
rst => HexVal[6]~reg0.PRESET 
rst => HexVal[5]~reg0.PRESET 
rst => HexVal[4]~reg0.PRESET 
rst => HexVal[3]~reg0.PRESET 
rst => HexVal[2]~reg0.PRESET 
rst => HexVal[1]~reg0.PRESET 
rst => HexVal[0]~reg0.PRESET 
HexVal[0] <= HexVal[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE 
HexVal[1] <= HexVal[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE 
HexVal[2] <= HexVal[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE 
HexVal[3] <= HexVal[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE 
HexVal[4] <= HexVal[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE 
HexVal[5] <= HexVal[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE 
HexVal[6] <= HexVal[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE 
 
 
|Time|DecDis:HC0 
DecVal[0] => Decoder0.IN3 
DecVal[1] => Decoder0.IN2 
DecVal[2] => Decoder0.IN1 
DecVal[3] => Decoder0.IN0 
clc => HexVal[6]~reg0.CLK 
clc => HexVal[5]~reg0.CLK 
clc => HexVal[4]~reg0.CLK 
clc => HexVal[3]~reg0.CLK 
clc => HexVal[2]~reg0.CLK 
clc => HexVal[1]~reg0.CLK 
clc => HexVal[0]~reg0.CLK 
rst => HexVal[6]~reg0.PRESET 
rst => HexVal[5]~reg0.PRESET 
rst => HexVal[4]~reg0.PRESET 
rst => HexVal[3]~reg0.PRESET 
rst => HexVal[2]~reg0.PRESET 
rst => HexVal[1]~reg0.PRESET 
rst => HexVal[0]~reg0.PRESET 
HexVal[0] <= HexVal[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE 
HexVal[1] <= HexVal[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE 
HexVal[2] <= HexVal[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE 
HexVal[3] <= HexVal[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE 
HexVal[4] <= HexVal[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE 
HexVal[5] <= HexVal[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE 
HexVal[6] <= HexVal[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE