www.pudn.com > uart_v11.zip > shiftreg.tdf

%////////////////////////////////////////////////////////////////////////////////////////////////////////// 
//                                                                                                       // 
//  PROJECT:      Parametized Shift Register with Asynchronous Load.                                     // 
//                Keith Willis                                                                           // 
//                Copyright © 1998. All Rights Reserved.                                                 // 
//                                                                                                       // 
//                You may use or distribute this module freely, provided you do not remove this          // 
//                copyright notice or modify the contents of this file.                                  // 
//                If you have questions or comments, feel free to contact me by email at                 // 
//                kcwillis@mech.eng.usyd.edu.au                                                          // 
//                                                                                                       // 
//  AUTHOR:       Keith Willis                                                                           // 
//                                                                                                       // 
//  MODULE:       ShiftReg.tdf                                                                           // 
//                                                                                                       // 
//  DESCRIPTION:  AHDL File for a Parametized Shift Register with Asynchronous Load.                     // 
//                                                                                                       // 
//  VERSION:      1.0                                                                                    // 
//                                                                                                       // 
//////////////////////////////////////////////////////////////////////////////////////////////////////////% 
 
TITLE "Parametized Shift Register with Asynchronous Load";  
 
 
%//////////////////////////// 
// USER-DEFINED PARAMETERS // 
////////////////////////////% 
 
PARAMETERS 
( 
 WIDTH=1, 
 SHIFT_MODE="ON", 
 MSB_FIRST="YES", 
 SYNCHRONIZER="NO" 
); 
 
 
%///////////////////// 
// INPUTS & OUTPUTS // 
/////////////////////% 
 
SUBDESIGN ShiftReg 
( 
 CLK						: INPUT; 
 D[(WIDTH-1)..0]			: INPUT=GND; 
 CLEAR						: INPUT=GND; 
 LOAD						: INPUT=GND; 
 ENABLE						: INPUT=VCC; 
 DIN						: INPUT=GND; 
 Q[(WIDTH-1)..0], DOUT		: OUTPUT; 
) 
 
 
%///////////////////////// 
// VARIABLE DEFINITIONS // 
/////////////////////////% 
 
VARIABLE 
 
 IF (SYNCHRONIZER=="YES") GENERATE 
  FF[WIDTH..0]				: DFFE; 
 ELSE GENERATE 
  FF[(WIDTH-1)..0]			: DFFE; 
 END GENERATE; 
 
 
%////////////////// 
// LOGIC SECTION // 
//////////////////% 
 
BEGIN 
 
 ASSERT (WIDTH > 0) 
 REPORT "Value of WIDTH parameter must be greater than 0" 
 SEVERITY ERROR; 
 
 ASSERT !(SHIFT_MODE=="ON" & WIDTH <= 1) 
 REPORT "Value of WIDTH parameter must be greater than 1 if using Shift Register Mode" 
 SEVERITY ERROR; 
 
 ASSERT !(SHIFT_MODE!="ON" & USED(DIN)) 
 REPORT "DIN is not required if not using Shift Register Mode" 
 SEVERITY WARNING; 
 
 ASSERT !(SHIFT_MODE!="ON" & USED(LOAD)) 
 REPORT "LOAD is not required if not using Shift Register Mode" 
 SEVERITY WARNING; 
 
 
 FF[].ena=ENABLE; 
 FF[].clk=CLK; 
 
IF (SHIFT_MODE=="ON") GENERATE 
 IF (SYNCHRONIZER=="YES") GENERATE 
  FF[WIDTH].clrn=!(LOAD # CLEAR); 
 END GENERATE; 
 
 FOR i IN 0 TO WIDTH-1 GENERATE 
  FF[i].prn=!(D[i] & LOAD); 
  FF[i].clrn=!(!D[i] & LOAD # CLEAR); 
 END GENERATE; 
 
 IF (MSB_FIRST=="YES") GENERATE 
  IF (SYNCHRONIZER=="YES") GENERATE 
   FF[0].d=DIN; 
   FOR i IN 1 TO WIDTH GENERATE 
    FF[i].d=FF[i-1].q; 
   END GENERATE; 
   DOUT=FF[WIDTH].q; 
  ELSE GENERATE 
   FF[0].d=DIN; 
   FOR i IN 1 TO WIDTH-1 GENERATE 
    FF[i].d=FF[i-1].q; 
   END GENERATE; 
   DOUT=FF[(WIDTH-1)].q; 
  END GENERATE; 
 ELSE GENERATE 
  IF (SYNCHRONIZER=="YES") GENERATE 
   FF[(WIDTH)].d=DIN; 
   FOR i IN 1 TO WIDTH GENERATE 
    FF[i-1].d=FF[i].q; 
   END GENERATE; 
   DOUT=FF[0].q; 
  ELSE GENERATE 
   FF[(WIDTH-1)].d=DIN; 
   FOR i IN 1 TO WIDTH-1 GENERATE 
    FF[i-1].d=FF[i].q; 
   END GENERATE; 
   DOUT=FF[0].q; 
  END GENERATE; 
 END GENERATE; 
 
ELSE GENERATE 
 FF[(WIDTH-1)..0].d=D[]; 
 FF[].clrn=!CLEAR; 
 IF (SYNCHRONIZER=="YES") GENERATE 
   DOUT=FF[WIDTH].q; 
  ELSE GENERATE 
   DOUT=FF[(WIDTH-1)].q; 
  END GENERATE; 
END GENERATE; 
 
Q[]=FF[(WIDTH-1)..0].q; 
 
END;