www.pudn.com > uart_v11.zip > clk_pdiv.tdf
%//////////////////////////////////////////////////////////////////////////////////////////////////////////
// //
// PROJECT: Programmable Clock Frequency Divider. //
// Keith Willis //
// Copyright © 1998. All Rights Reserved. //
// //
// You may use or distribute this module freely, provided you do not remove this //
// copyright notice or modify the contents of this file. //
// If you have questions or comments, feel free to contact me by email at //
// kcwillis@mech.eng.usyd.edu.au //
// //
// AUTHOR: Keith Willis //
// //
// MODULE: Clk_PDiv.tdf //
// //
// DESCRIPTION: AHDL File for Programmable Clock Frequency Divider. //
// //
// VERSION: 1.0 //
// //
// NOTE: This design is based in part on the VAR_DIV module designed by Rune Baeverrud. //
// //
//////////////////////////////////////////////////////////////////////////////////////////////////////////%
TITLE "Programmable Clock Frequency Divider";
%//////////////////
// INCLUDE FILES //
//////////////////%
INCLUDE "lpm_counter";
INCLUDE "lpm_compare";
INCLUDE "lpm_dff";
%////////////////////////////
// USER-DEFINED PARAMETERS //
////////////////////////////%
PARAMETERS
(
WIDTH = 1
);
%/////////////////////
// INPUTS & OUTPUTS //
/////////////////////%
SUBDESIGN clk_pdiv
(
CLK, D[WIDTH-1..0] : INPUT;
ENABLE : INPUT = VCC;
RESET : INPUT = GND;
OUT, Q[WIDTH-1..0] : OUTPUT;
)
%/////////////////////////
// VARIABLE DEFINITIONS //
/////////////////////////%
VARIABLE
COUNT : NODE;
%//////////////////
// LOGIC SECTION //
//////////////////%
BEGIN
ASSERT (WIDTH > 0)
REPORT "Value of WIDTH parameter must be greater than 0"
SEVERITY ERROR;
COUNT = LPM_COMPARE(Q[], D[],,)
WITH (LPM_WIDTH=WIDTH)
RETURNS (.aeb);
Q[] = LPM_COUNTER (0, CLK, ENABLE,,, RESET,,,, COUNT,,,)
WITH (LPM_WIDTH=WIDTH)
RETURNS (.q[]);
OUT = LPM_DFF (COUNT, CLK, ENABLE,,,,,,,,)
WITH (LPM_WIDTH=1)
RETURNS (.q[]);
END;