www.pudn.com > hdl.rar > writeData.v
/*module writeData(
clk16M,
arst,
// rb,
enable,
wrdfinish,
datain,
wr,
cle,
// re,
data
// sel
);
input
clk16M,
arst,
// rb,
enable,
wrdfinish;
input [7:0]
datain;
output
wr,
cle;
// re,
// sel;
output [7:0]
data;
reg
we,
wetemp,
wecmd,
cle,
// re,
// sel,
state;
reg [2:0]
state1;
reg [7:0]
data,
dataout,
cmdata;
wire [7:0]
temp;
assign wr = wetemp & wecmd;
always @(posedge clk16M or negedge arst)
begin
if(arst == 0)
begin
dataout <= 8'd0;
we <= 1'b1;
end
else if(enable == 1)
begin
case(state)
1'b0:
begin
we <= 1'b0;
dataout <= datain;
end
1'b1:
begin
we <= 1'b1;
end
endcase
end//else if(enable == 1)
end//always
assign temp = (enable == 1'b1)? dataout : cmdata;
always @(posedge clk16M or negedge arst)
begin
if(arst == 0)
begin
data <= 8'd0;
wetemp <= 1'b1;
end
else
begin
data <= temp;
wetemp <= we;
end
end
always @(posedge clk16M or negedge arst)
begin
if(arst == 0)
begin
state <= 1'b0;
end
else if(enable == 1)
begin
state <= ~state;
end
end//always
always @(posedge clk16M or negedge arst)
begin
if(arst == 0)
begin
cle <= 1'b0;
wecmd <= 1'b1;
//re <= 1'b1;
//sel <= 1'b0;
end
else
begin
case(state1)
3'd1:
begin
cle <= 1'b1;
end
3'd2:
begin
wecmd <= 1'b0; //дÃüÁî10H
cmdata <= 8'h10;
end
3'd3:
begin
wecmd <= 1'b1;
end
3'd4:
cle <= 1'b0;*/
/* 4'd7:
begin
wecmd <= 1'b0;
end
4'd8:
wecmd <= 1'b1;
4'd9:
begin
cle <= 1'b0;
end
4'd10:
begin
re <= 1'b0;
end
4'd11:
begin
re <= 1'b1;
sel <= 1'b1;
end*/
/*endcase
end//else
end//always
always @(posedge clk16M or negedge arst)
begin
if(arst == 0)
begin
state1 <= 3'd0;
end
else// if(rb == 1)
begin
case(state1)
3'd0:
begin
state1[0] <= wrdfinish;
end
3'd1:
state1 <= 3'd2;
3'd2:
state1 <= 3'd3;
3'd3:
state1 <= 3'd4;
3'd4:
state1 <= 3'd0;*/
/* 4'd4:
state1 <= 4'd5;
4'd5:
state1 <= 4'd6;
4'd6:
state1 <= 4'd7;
4'd7:
state1 <= 4'd8;
4'd8:
state1 <= 4'd9;
4'd9:
state1 <= 4'd10;
4'd10:
state1 <= 4'd11;
4'd11:
state1 <= 4'd0;*/
/*endcase
end//else
end//always
endmodule*/
module writeData(
clk24M,
arst,
datastart,
fifodata,
fiforen,
datawe,
datacle,
flashdata,
datafinish
);
input
clk24M,
arst,
datastart;
input [15:0]
fifodata;
output
fiforen,
datawe,
datacle,
datafinish;
output [7:0]
flashdata;
reg
fiforen,
datawe,
//we,
datacle,
datafinish;
reg [7:0]
flashdata;
reg [7:0]
cnt;
reg
cntfull;
reg [3:0]
state;
always @(posedge clk24M or negedge arst)
begin
if(arst == 0)
begin
//fiforen <= 1'b0;
//datacle <= 1'b0;
//we <= 1'b1;
flashdata <= 8'd0;
end
else
begin
case(state)
//4'd1:
//fiforen <= 1'b0;
//4'd2:
//begin
//fiforen <= 1'b1;
//we <= 1'b0;
//end
4'd3:
begin
//we <= 1'b1;
//fiforen <= 1'b0;
flashdata <= fifodata[7:0];
end
//4'd4:
//we <= 1'b0;
4'd5:
begin
//fiforen <= 1'b1;
//we <= 1'b1;
flashdata <= fifodata[15:8];
end
//4'd6:
//begin
//fiforen <= 1'b0;
//we <= 1'b0;
//end
//4'd7:
//begin
//we <= 1'b1;
//flashdata <= fifodata[7:0];
//end
//4'd8:
//we <= 1'b0;//
//4'd9:
//begin
//we <= 1'b1;
//flashdata <= {4'd0,fifodata[11:8]};
//flashdata <= fifodata[15:8];
//end
//4'd11:
//begin
//we <= 1'b0;
//datacle <= 1'b1;
//end
4'd9:
begin
//we <= 1'b1;
flashdata <= 8'h10;
end
//4'd14:
//datacle <= 1'b0;
endcase
end
end
always @(posedge clk24M or negedge arst)
begin
if(arst == 0)
begin
datawe <= 1'b1;
end
else
begin
//datawe <= (((state[3] & state[2]) | (~state[3] & state[0])) | (~state[1] & state[0])) |
//(((state[3] & state[1]) & (state[0])) | (~(state[3] | state[2] | state[1])));
//datawe <= ((~state[3]) & state[2] &(~state[0]))| (state[3] & state[1]) | ((~state[3])&(~state[2])&((~state[1])|(~state[0])))|
//(state[3]&(~state[2])&(~state[1])&(~state[0])) | (state[3]&state[2]&(~state[1])&state[0]);
//datawe <= state[3] | ((~state[3])&((~state[1])|(~state[0])));
datawe <= ((~state[3])&(~state[2])&((~state[1])|(~state[0])))|
((~state[3])&(state[2])&(~state[1])&(~state[0]))|
((~state[3])&(state[2])&(state[1]))|
((state[3])&(~state[2])&(~state[1])&(~state[0]))|
((state[3])&((state[2])|(state[1])));
/*case(state)
4'd2:
we <= 1'b0; 1
4'd3:
we <= 1'b1; 0
4'd4:
we <= 1'b0; 1
4'd5:
we <= 1'b1; 0
4'd6:
we <= 1'b0; 1
4'd7:
we <= 1'b1; 1
4'd8:
we <= 1'b0; 1
4'd9:
we <= 1'b1; 0
4'd10:
we <= 1
4'd11:
we <= 1'b0; 1
4'd12:
we <= 1'b1; 1
4'd13:
we <= 1
endcase*/
end
end
always @(posedge clk24M or negedge arst)
begin
if(arst == 0)
begin
fiforen <= 1'b0;
end
else
begin
//fiforen <= (~(state[3] | state[1])) & state[0];
fiforen <= ((~state[3]) & (~state[2]) & state[1] & (~state[0]));
/*case(state)
4'd1: //0001
fiforen <= 1'b0;
4'd2: //0010
fiforen <= 1'b1;
4'd3: //0011
fiforen <= 1'b0;
//4'd6: //0110
fiforen <= 1'b0;
endcase*/
end
end
always @(posedge clk24M or negedge arst)
begin
if(arst == 0)
begin
datacle <= 1'b0;
end
else
begin
//datacle <= (state[3] & state[1] & state[0]) | ((state[3] & state[2]) & (~state[1]));
//datacle <= ((~state[3])&state[2]&state[1])|(state[3]&(~state[2])&(~state[1])&(~state[0]));
datacle <= (state[3]&(~state[2])&(state[1]|state[0]));
/*case(state)
4'd6: //1011 1100 1101
datacle <= 1'b1;
4'd9: //1110
datacle <= 1'b0;
endcase*/
end
end
/*always @(posedge clk24M or negedge arst)
begin
if(arst == 0)
begin
datawe <= 1'b1;
end
else
begin
datawe <= we;
end
end*/
always @(posedge clk24M or negedge arst)
begin
if(arst == 0)
begin
datafinish <= 1'b1;
state <= 4'd0;
end
else
begin
case(state)
4'd0:
state[0] <= datastart;
4'd1:
state <= 4'd2;
4'd2:
state <= 4'd3;
4'd3:
state <= 4'd4;
4'd4:
state <= 4'd5;
4'd5:
state <= 4'd6;
4'd6:
state <= 4'd7;
4'd7:
begin
if(cntfull)
begin
state <= 4'd2;
end
else
begin
state <= 4'd8;
end
end
4'd8:
state <= 4'd9;
4'd9:
state <= 4'd10;
4'd10:
begin
datafinish <= 1'b0;
state <= 4'd11;
end
4'd11:
begin
datafinish <= 1'b1;
state <= 4'd0;
end
endcase
end
end
always @(posedge clk24M or negedge arst)
begin
if(arst == 0)
begin
cnt <= 8'd0;
end
else
begin
if(fiforen)
begin
cnt <= cnt + 1'b1;
end
end
end
always @(posedge clk24M or negedge arst)
begin
if(arst == 0)
begin
cntfull <= 1'b0;
end
else
begin
cntfull <= ((cnt[7] | cnt[6]) | (cnt[5] | cnt[4])) | ((cnt[3] | cnt[2]) | (cnt[1] | cnt[0]));
end//
end
endmodule