www.pudn.com > hdl.rar > flashwritefifo.v

// flashwritefifo.v 
module flashwritefifo( 
    clk32M, 
    arst, 
    rb1, 
    AFULL1, 
    we1, 
    re1, 
    cle1, 
    ale1, 
    ce1, 
    wp1, 
    fifo1data, 
    data1, 
    fifo1ren 
    ); 
 
    input 
        clk32M, 
        arst, 
        rb1, 
        AFULL1; 
    input [7:0] 
        fifo1data, 
    output 
        we1, 
        re1, 
        cle1, 
        ale1, 
        ce1, 
        wp1, 
        fifo1ren; 
    output [7:0]       
        data1; 
    wire 
        cmdstart, 
        cmdfinish, 
        datastart, 
        cmdwe, 
        cmdcle, 
        cmdale, 
        sel, 
        datawe, 
        datacle; 
    wire [15:0] 
        addr; 
    wire [7:0] 
        cmdata, 
        flashdata; 
 
    assign re1 = 1'b1; 
    assign ce1 = 1'b0; 
    assign wp1 = 1'b1; 
 
    flashWrCon fwc1(clk32M,arst,rb1,AFULL1,cmdstart,cmdfinish,datastart,addr); 
    writeCmd wc1(clk32M,arst,addr,cmdstart,cmdfinish,cmdwe,cmdcle,cmdale,sel,cmdata); 
    writesdlcdata wsd(clk32M,arst,datastart,fifo1data,fifo1ren,datawe,datacle,flashdata); 
    condata cd1(clk32M,arst,cmdwe,cmdale,cmdcle,cmdata,sel,datawe,datacle,flashdata,we1,ale1,cle1,data1); 
 
endmodule