www.pudn.com > hdl.rar > condata.v

/*module condata( 
	clk16M, 
	arst, 
//	sel, 
	cmdata, 
	data, 
	cle, 
	datacle, 
	ale, 
//	re, 
	cmdwe, 
	datawe, 
	start, 
	finish, 
	flashdata, 
//	rd, 
	wr, 
	fcle, 
	fale 
//	sign 
	); 
	 
	input 
		clk16M, 
		arst, 
//		sel, 
		cle, 
		datacle, 
		ale, 
//		re, 
		cmdwe, 
		datawe, 
		start, 
		finish; 
	input [7:0] 
		cmdata, 
		data; 
	output [7:0] 
		flashdata; 
	output 
//		rd, 
		wr, 
		fcle, 
		fale; 
//		sign; 
		 
	reg 
//		rd, 
//		retemp, 
		wr, 
		fcle, 
		fale, 
//		sign, 
//		rdposedge, 
		mux; 
	reg [7:0] 
		datatemp; 
	wire [7:0] 
		muxdata; 
//		rdata; 
	wire 
		wetemp, 
		cletemp; 
 
	always @(posedge clk16M or negedge arst) 
	begin 
		if(arst == 0) 
		begin 
			mux <= 1'b0; 
		end 
		else 
		begin 
			if(start == 1) 
				mux <= 1'b0; 
			else if(finish == 1) 
				mux <= 1'b1; 
		end 
	end 
	 
	assign muxdata = (mux == 0)? cmdata : data; 
	assign wetemp = cmdwe & datawe; 
	assign cletemp = cle | datacle; 
	 
	always @(posedge clk16M or negedge arst) 
	begin 
		if(arst == 0) 
		begin 
			//rd <= 1'b1; 
			//retemp <= 1'b1; 
			wr <= 1'b1; 
			fcle <= 1'b0; 
			fale <= 1'b0; 
			datatemp <= 8'd0; 
		end 
		else 
		begin 
			//rd <= re; 
			//retemp <= rd; 
			wr <= wetemp; 
			fcle <= cletemp; 
			fale <= ale; 
			datatemp <= muxdata; 
		end 
	end*/ 
	 
/*	always @(posedge clk16M or negedge arst) 
	begin 
		if(arst == 0) 
		begin 
			rdposedge <= 1'b0; 
		end 
		else 
		begin 
			if(~retemp & rd) 
				rdposedge <= 1'b1; 
		end 
	end*/ 
	 
	//assign flashdata = datatemp;//(sel)? 8'dz : datatemp; 
	//assign rdata = (~retemp & rd)? flashdata : 8'dz; 
	 
/*	always @(posedge clk16M or negedge arst) 
	begin 
		if(arst == 0) 
		begin 
			sign <= 1'b1; 
		end 
		else 
		begin 
			sign <= flashdata[0]; 
		end 
	end 
	*/ 
//endmodule 
module condata( 
	clk24M, 
	arst, 
	cmdwe, 
	cmdale, 
	cmdcle, 
	cmdata, 
	sel, 
	datawe, 
	datacle, 
	flashdata, 
	we, 
	ale, 
	cle, 
	data 
	); 
 
input 
	clk24M, 
	arst, 
	cmdwe, 
	cmdale, 
	cmdcle, 
	sel, 
	datawe, 
	datacle; 
input [7:0] 
	cmdata, 
	flashdata; 
output 
	we, 
	ale, 
	cle; 
output [7:0] 
	data; 
reg [7:0] 
	data; 
reg 
	we, 
	cle, 
	ale; 
	 
always @(posedge clk24M or negedge arst) 
begin 
	if(arst == 0) 
	begin 
		data <= 8'd0; 
	end 
	else 
	begin 
		if(sel) 
		begin 
			data <= flashdata; 
		end 
		else 
		begin 
			data <= cmdata; 
		end 
	end 
end 
always @(posedge clk24M or negedge arst) 
begin 
	if(arst == 0) 
	begin 
		we <= 1'b1; 
		cle <= 1'b0; 
		ale <= 1'b0; 
	end 
	else 
	begin 
		we <= cmdwe & datawe; 
		ale <= cmdale; 
		cle <= cmdcle | datacle; 
	end 
end 
/*assign we = cmdwe & datawe; 
assign ale = cmdale; 
assign cle = cmdcle | datacle;*/ 
	 
 
endmodule