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;=========================================== 
; NAME: OPTION.A 
; DESC: Configuration options for .S files 
; HISTORY: 
; 02.28.2002: ver 0.0 
; 03.11.2003: ver 0.0	attached for 2440. 
; jan E, 2004: ver0.03  modified for 2440A01. 
;=========================================== 
 
;Start address of each stacks, 
_STACK_BASEADDRESS	EQU 0x33ff8000 
_MMUTT_STARTADDRESS	EQU 0x33ff8000 
_ISR_STARTADDRESS	EQU 0x33ffff00 
 
		GBLL 	PLL_ON_START 
PLL_ON_START	SETL 	{TRUE} 
 
 
		GBLL	ENDIAN_CHANGE 
ENDIAN_CHANGE	SETL	{FALSE} 
 
		GBLA	ENTRY_BUS_WIDTH 
ENTRY_BUS_WIDTH	SETA	16 
 
 
;BUSWIDTH = 16,32 
		GBLA    BUSWIDTH	;max. bus width for the GPIO configuration 
BUSWIDTH	SETA    32 
 
		GBLA	UCLK 
UCLK	SETA	48000000 
 
		GBLA	XTAL_SEL 
		GBLA	FCLK 
		GBLA	CPU_SEL 
 
;(1) Select CPU		 
;CPU_SEL	SETA	32440000	; 32440000:2440X. 
CPU_SEL	SETA	32440001	; 32440001:2440A 
 
;(2) Select XTaL 
XTAL_SEL	SETA	12000000	;hzh 
;XTAL_SEL	SETA	16934400 
 
;(3) Select FCLK 
;FCLK		SETA	304000000 
;FCLK		SETA	296352000 
;FCLK		SETA	271500000 
;FCLK		SETA	100000000	;hzh 
;FCLK		SETA	200000000	;hzh 
FCLK		SETA	400000000	;hzh 
 
 
;(4) Select Clock Division (Fclk:Hclk:Pclk) 
;FCLK = 100000000 
;CLKDIV_VAL	EQU	1	; 0=1:1:1, 1=1:1:2, 2=1:2:2, 3=1:2:4, 4=1:4:4, 5=1:4:8, 6=1:3:3, 7=1:3:6. 
;FCLK = 200000000 
;CLKDIV_VAL	EQU	3	; 0=1:1:1, 1=1:1:2, 2=1:2:2, 3=1:2:4, 4=1:4:4, 5=1:4:8, 6=1:3:3, 7=1:3:6. 
;FCLK = 400000000 
CLKDIV_VAL	EQU	5	; 0=1:1:1, 1=1:1:2, 2=1:2:2, 3=1:2:4, 4=1:4:4, 5=1:4:8, 6=1:3:3, 7=1:3:6. 
;FCLK = 304000000 or 271500000 
;CLKDIV_VAL	EQU	7	; 0=1:1:1, 1=1:1:2, 2=1:2:2, 3=1:2:4, 4=1:4:4, 5=1:4:8, 6=1:3:3, 7=1:3:6. 
 
 [ XTAL_SEL = 12000000 
  
	[ FCLK = 271500000 
M_MDIV		EQU	173		;Fin=12.0MHz Fout=271.5MHz 
M_PDIV		EQU	2 
		[ CPU_SEL = 32440001 
M_SDIV		EQU	2		; 2440A 
   		| 
M_SDIV		EQU	1		; 2440X 
   		] 
	] 
	 
	[ FCLK = 304000000 
M_MDIV		EQU	68		;Fin=12.0MHz Fout=304.8MHz 
M_PDIV		EQU	1 
		[ CPU_SEL = 32440001 
M_SDIV		EQU	1		; 2440A 
		| 
M_SDIV		EQU	0		; 2440X 
		] 
	] 
 
	[ FCLK = 100000000 
M_MDIV		EQU	42		;Fin=12.0MHz Fout=100MHz 
M_PDIV		EQU	4 
		[ CPU_SEL = 32440001 
M_SDIV		EQU	1		; 2440A 
		| 
M_SDIV		EQU	0		; 2440X 
		] 
	] 
 
	[ FCLK = 200000000 
M_MDIV		EQU	92		;Fin=12.0MHz Fout=200MHz 
M_PDIV		EQU	4 
		[ CPU_SEL = 32440001 
M_SDIV		EQU	1		; 2440A 
		| 
M_SDIV		EQU	0		; 2440X 
		] 
	] 
 
	[ FCLK = 400000000 
M_MDIV		EQU	92		;Fin=12.0MHz Fout=400MHz 
M_PDIV		EQU	1 
		[ CPU_SEL = 32440001 
M_SDIV		EQU	1		; 2440A 
		| 
M_SDIV		EQU	0		; 2440X 
		] 
	] 
	 
	[ UCLK = 48000000 
U_MDIV		EQU	56		;Fin=12.0MHz Fout=48MHz 
U_PDIV		EQU	2 
		[ CPU_SEL = 32440001 
U_SDIV		EQU	2		; 2440A 
   		| 
U_SDIV		EQU	1		; 2440X 
   		] 
	] 
	[ UCLK = 96000000 
U_MDIV		EQU	56		;Fin=12.0MHz Fout=96MHz 
U_PDIV		EQU	2 
		[ CPU_SEL = 32440001 
U_SDIV		EQU	1		; 2440A 
   		| 
U_SDIV		EQU	0		; 2440X 
   		] 
 
	] 
 
  |	; else if XTAL_SEL = 16.9344Mhz 
 
	[ FCLK = 266716800 
M_MDIV		EQU	118	;Fin=16.9344MHz 
M_PDIV		EQU	2 
		[ CPU_SEL = 32440001 
M_SDIV		EQU	2		; 2440A 
		| 
M_SDIV		EQU	1		; 2440X 
		] 
	] 
	 
	[ FCLK = 296352000 
M_MDIV		EQU	97	;Fin=16.9344MHz 
M_PDIV		EQU	1 
		[ CPU_SEL = 32440001 
M_SDIV		EQU	2		; 2440A 
		| 
M_SDIV		EQU	1		; 2440X 
		] 
	] 
	[ FCLK = 541900800 
M_MDIV		EQU	120	;Fin=16.9344MHz 
M_PDIV		EQU	2 
		[ CPU_SEL = 32440001 
M_SDIV		EQU	1		; 2440A 
		| 
M_SDIV		EQU	0		; 2440X 
		] 
	] 
	 
	[ UCLK = 48000000 
U_MDIV		EQU	60	;Fin=16.9344MHz Fout=48MHz 
U_PDIV		EQU	4 
		[ CPU_SEL = 32440001 
U_SDIV		EQU	2		; 2440A 
   		| 
U_SDIV		EQU	1		; 2440X 
   		] 
   	] 
	[ UCLK = 96000000 
U_MDIV		EQU	60	;Fin=16.9344MHz Fout=96MHz 
U_PDIV		EQU	4 
		[ CPU_SEL = 32440001 
U_SDIV		EQU	1		; 2440A 
   		| 
U_SDIV		EQU	0		; 2440X 
   		] 
	] 
	 
   ]	; end of if XTAL_SEL = 12000000. 
   
 
 
 
	END