www.pudn.com > OSBDM08.zip > MC68HC908JB8.c
/* Based on CPU DB MC68HC908JB8, version 2.87.031 (RegistersPrg V1.061) */ /* DataSheet : manual revision not specified */ #include/* * * * * 8-BIT REGISTERS * * * * * * * * * * * * * * * */ volatile BRKSCRSTR _BRKSCR; /* Break Status and Control Register */ volatile BSRSTR _BSR; /* Break Status Register */ volatile CONFIGSTR _CONFIG; /* Configuration Register */ volatile COPCTLSTR _COPCTL; /* COP Control Register */ volatile DDRASTR _DDRA; /* Data Direction Register A */ volatile DDRBSTR _DDRB; /* Data Direction Register B */ volatile DDRCSTR _DDRC; /* Data Direction Register C */ volatile DDRDSTR _DDRD; /* Data Direction Register D */ volatile DDRESTR _DDRE; /* Data Direction Register E */ volatile FLBPRSTR _FLBPR; /* FLASH Block Protect Register */ volatile FLCRSTR _FLCR; /* FLASH Control Register */ volatile INT1STR _INT1; /* Interrupt Status Register 1 */ volatile IOCRSTR _IOCR; /* IRQ Option Register */ volatile ISCRSTR _ISCR; /* IRQ Status and Control Register */ volatile KBIERSTR _KBIER; /* Keyboard Interrrupt Enable Register KBIER */ volatile KBSCRSTR _KBSCR; /* Keyboard Status and Control Register */ volatile POCRSTR _POCR; /* Port Option Control Register */ volatile PTASTR _PTA; /* Port A Data Register */ volatile PTBSTR _PTB; /* Port B Data Register */ volatile PTCSTR _PTC; /* Port C Data Register */ volatile PTDSTR _PTD; /* Port D Data Register */ volatile PTESTR _PTE; /* Port E Data Register */ volatile RSRSTR _RSR; /* Reset Status Register */ volatile SBFCRSTR _SBFCR; /* SIM Break Flag Control Register */ volatile TSCSTR _TSC; /* TIM Status and Control Register TSC */ volatile TSC0STR _TSC0; /* TIM Channel 0 Status and Control Register */ volatile TSC1STR _TSC1; /* TIM Channel 1 Status and Control Register */ volatile UADDRSTR _UADDR; /* USB Address Register */ volatile UCR0STR _UCR0; /* USB Control Register 0 */ volatile UCR1STR _UCR1; /* USB Control Register 1 */ volatile UCR2STR _UCR2; /* USB Control Register 2 */ volatile UCR3STR _UCR3; /* USB Control Register 3 */ volatile UCR4STR _UCR4; /* USB Control Register 4 */ volatile UE0D0STR _UE0D0; /* USB Endpoint 0 Data Register 0 */ volatile UE0D1STR _UE0D1; /* USB Endpoint 0 Data Register 1 */ volatile UE0D2STR _UE0D2; /* USB Endpoint 0 Data Register 2 */ volatile UE0D3STR _UE0D3; /* USB Endpoint 0 Data Register 3 */ volatile UE0D4STR _UE0D4; /* USB Endpoint 0 Data Register 4 */ volatile UE0D5STR _UE0D5; /* USB Endpoint 0 Data Register 5 */ volatile UE0D6STR _UE0D6; /* USB Endpoint 0 Data Register 6 */ volatile UE0D7STR _UE0D7; /* USB Endpoint 0 Data Register 7 */ volatile UE1D0STR _UE1D0; /* USB Endpoint 1 Data Register 0 */ volatile UE1D1STR _UE1D1; /* USB Endpoint 1 Data Register 1 */ volatile UE1D2STR _UE1D2; /* USB Endpoint 1 Data Register 2 */ volatile UE1D3STR _UE1D3; /* USB Endpoint 1 Data Register 3 */ volatile UE1D4STR _UE1D4; /* USB Endpoint 1 Data Register 4 */ volatile UE1D5STR _UE1D5; /* USB Endpoint 1 Data Register 5 */ volatile UE1D6STR _UE1D6; /* USB Endpoint 1 Data Register 6 */ volatile UE1D7STR _UE1D7; /* USB Endpoint 1 Data Register 7 */ volatile UE2D0STR _UE2D0; /* USB Endpoint 2 Data Register 0 */ volatile UE2D1STR _UE2D1; /* USB Endpoint 2 Data Register 1 */ volatile UE2D2STR _UE2D2; /* USB Endpoint 2 Data Register 2 */ volatile UE2D3STR _UE2D3; /* USB Endpoint 2 Data Register 3 */ volatile UE2D4STR _UE2D4; /* USB Endpoint 2 Data Register 4 */ volatile UE2D5STR _UE2D5; /* USB Endpoint 2 Data Register 5 */ volatile UE2D6STR _UE2D6; /* USB Endpoint 2 Data Register 6 */ volatile UE2D7STR _UE2D7; /* USB Endpoint 2 Data Register 7 */ volatile UIR0STR _UIR0; /* USB Interrupt Register 0 */ volatile UIR1STR _UIR1; /* USB Interrupt Register 1 */ volatile UIR2STR _UIR2; /* USB Interrupt Register 2 */ volatile USR0STR _USR0; /* USB Status Register 0 */ volatile USR1STR _USR1; /* USB Status Register 1 */ /* * * * * 16-BIT REGISTERS * * * * * * * * * * * * * * * */ volatile BRKSTR _BRK; /* Break Address Register */ volatile T1CNTSTR _TCNT; /* TIM Counter Register */ volatile T1CH0STR _TCH0; /* TIM Channel 0 Register */ volatile T1CH1STR _TCH1; /* TIM Channel 1 Register */ volatile T1MODSTR _TMOD; /* TIM Counter Modulo Register */ /* EOF */