www.pudn.com > S3C2440_uCos-II.rar > 2440init.s
;=========================================
;
;=========================================
GET Option.inc
GET memcfg.inc
GET 2440addr.inc
;====================================
; MMU Cache/TLB/etc on/off functions
;====================================
R1_I EQU (1<<12)
R1_C EQU (1<<2)
R1_A EQU (1<<1)
R1_M EQU (1)
R1_iA EQU (1<<31)
R1_nF EQU (1<<30)
BIT_SELFREFRESH EQU (1<<22)
;Pre-defined constants
USERMODE EQU 0x10
FIQMODE EQU 0x11
IRQMODE EQU 0x12
SVCMODE EQU 0x53
ABORTMODE EQU 0x17
UNDEFMODE EQU 0x1b
MODEMASK EQU 0x1f
NOINT EQU 0xc0
;The location of stacks
UserStack EQU (_STACK_BASEADDRESS-0x5000)
SVCStack EQU (_STACK_BASEADDRESS-0x4000)
UndefStack EQU (_STACK_BASEADDRESS-0x3000)
AbortStack EQU (_STACK_BASEADDRESS-0x2000)
IRQStack EQU (_STACK_BASEADDRESS-0x1000)
FIQStack EQU (_STACK_BASEADDRESS-0x0)
MACRO
$HandlerLabel HANDLER $HandleLabel
$HandlerLabel
sub sp,sp,#4 ;decrement sp(to store jump address)
stmfd sp!,{r0} ;PUSH the work register to stack(lr does't push because it return to original address)
ldr r0,=$HandleLabel;load the address of HandleXXX to r0
ldr r0,[r0] ;load the contents(service routine start address) of HandleXXX
str r0,[sp,#4] ;store the contents(ISR) of HandleXXX to stack
ldmfd sp!,{r0,pc} ;POP the work register and pc(jump to ISR)
MEND
IMPORT |Image$$RO$$Base| ; Base of ROM code
IMPORT |Image$$RO$$Limit| ; End of ROM code (=start of ROM data)
IMPORT |Image$$RW$$Base| ; Base of RAM to initialise
IMPORT |Image$$RW$$Limit| ; End of RAM to initialise
IMPORT |Image$$ZI$$Base| ; Base and limit of area
IMPORT |Image$$ZI$$Limit| ; to zero initialise
IMPORT Main ; The main entry of mon program
IMPORT __C_Inits ;
;IMPORT nand_init
IMPORT nand_read_ll
AREA Init,CODE,READONLY
ENTRY
EXPORT ImageEntryPoint
ImageEntryPoint
b ResetHandler
b HandlerUndef ;handler for Undefined mode
b HandlerSWI ;handler for SWI interrupt
b HandlerPabort ;handler for PAbort
b HandlerDabort ;handler for DAbort
b Auto_Reset ;reserved
b HandlerIRQ ;handler for IRQ interrupt
b HandlerFIQ ;handler for FIQ interrupt
;HandlerIRQ HANDLER HandleIRQ
HandlerIRQ
sub sp,sp,#4 ;reserved for PC
stmfd sp!,{r8-r9}
ldr r9,=INTOFFSET
ldr r9,[r9]
ldr r8,=HandleEINT0
add r8,r8,r9,lsl #2
ldr r8,[r8]
str r8,[sp,#8]
ldmfd sp!,{r8-r9,pc}
HandlerFIQ HANDLER HandleFIQ
HandlerUndef HANDLER HandleUndef
HandlerSWI HANDLER HandleSWI
HandlerDabort HANDLER HandleDabort
HandlerPabort HANDLER HandlePabort
EXPORT Auto_Reset
Auto_Reset
ldr r0,=WTCON ;watch dog disable
ldr r1,=0x8021
str r1,[r0]
b .
LTORG
EXPORT SWI_UNF_Def
EXPORT IRQ_FIQ_PABT_Def
EXPORT DABT_Def
SWI_UNF_Def
movs pc,lr
IRQ_FIQ_PABT_Def
subs pc,lr,#4
DABT_Def
subs pc,lr,#8
;=======
; ENTRY
;=======
ResetHandler
ldr r0,=WTCON ;watch dog disable
mov r1,#0x0
str r1,[r0]
ldr r0,=INTMSK
ldr r1,=0xffffffff ;all interrupt disable
str r1,[r0]
ldr r0,=SRCPND
str r1,[r0]
ldr r0,=INTPND
str r1,[r0]
ldr r0,=INTSUBMSK
ldr r1,=0x7fff ;all sub interrupt disable, 2002/04/10
str r1,[r0]
;ldr r0,=SUBSRCPND
;str r1,[r0]
;To reduce PLL lock time, adjust the LOCKTIME register.
;ldr r0,=LOCKTIME
;ldr r1,=0xffffff
;str r1,[r0]
mov r1, #CLK_CTL_BASE
ldr r2, clock_locktime
str r2, [r1, #oLOCKTIME]
mov r1, #CLK_CTL_BASE
ldr r2, clkdivn_value
str r2, [r1, #oCLKDIVN]
mrc p15, 0, r1, c1, c0, 0 ; read ctrl register
orr r1, r1, #0xc0000000 ; Asynchronous
mcr p15, 0, r1, c1, c0, 0 ; write ctrl register
mov r1, #CLK_CTL_BASE
ldr r2, mpll_value ; clock default
;ldr r2, mpll_value_USER ; clock user set
str r2, [r1, #oMPLLCON]
;Set memory control registers
adr r0,SMRDATA
ldr r1,=BWSCON ;BWSCON Address
add r2, r0, #52 ;End address of SMRDATA
0
ldr r3, [r0], #4
str r3, [r1], #4
cmp r0, r2
bcc %B0
;Initialize stacks
bl InitStacks
; InitUART
; set GPIO for UART
mov r1, #GPIO_CTL_BASE
add r1, r1, #oGPIO_H
ldr r2, gpio_con_uart
str r2, [r1, #oGPIO_CON]
ldr r2, gpio_up_uart
str r2, [r1, #oGPIO_UP]
ldr r1, SerBase
mov r2, #0x0
str r2, [r1, #oUFCON]
str r2, [r1, #oUMCON]
mov r2, #0x3
str r2, [r1, #oULCON]
ldr r2, =0x245
str r2, [r1, #oUCON]
UART_BRD EQU ((UART_PCLK / (UART_BAUD_RATE*16)) - 1)
mov r2, #UART_BRD
str r2, [r1, #oUBRDIV]
mov r3, #100
1 subs r3, r3, #0x1
bne %B1
;bl nand_init
; reset NAND
;nand_init
mov r1, #NAND_CTL_BASE
ldr r2, =( (7<<12)|(7<<8)|(7<<4)|(0<<0) )
str r2, [r1, #oNFCONF]
ldr r2, [r1, #oNFCONF]
ldr r2, =( (1<<4)|(0<<1)|(1<<0) ) ; Active low CE Control
str r2, [r1, #oNFCONT]
ldr r2, [r1, #oNFCONT]
ldr r2, =(0x6) ; RnB Clear
str r2, [r1, #oNFSTAT]
ldr r2, [r1, #oNFSTAT]
mov r2, #0xff ; RESET command
strb r2, [r1, #oNFCMD]
mov r3, #0 ; wait
1 add r3, r3, #0x1
cmp r3, #0xa
blt %B1
2 ldr r2, [r1, #oNFSTAT] ; wait ready
tst r2, #0x4
beq %B2
ldr r2, [r1, #oNFCONT]
orr r2, r2, #0x2 ; Flash Memory Chip Disable
str r2, [r1, #oNFCONT]
;Copy ROM code to SDRAM
adr r0, ImageEntryPoint
ldr r2, =|Image$$RW$$Base| ; and RAM copy
ldr r3, =|Image$$ZI$$Base|
sub r2,r3,r2
ldr r3, =|Image$$RO$$Limit|
ldr r1, =|Image$$RO$$Base| ; Get pointer to ROM data
add r2,r2,r3
cmp r0,#0
bne %F0
ldr r3,=BWSCON
ldr r3,[r3]
ands r3,r3,#0x06
bne %F1
; boot from NAND flash
mov r0,r1
sub r2,r2,r1
mov r1,#0
ldr lr, =On_The_Ram
b nand_read_ll
; boot from NOR flash
0
cmp r0,r1
beq %F2
1
cmp r1, r2 ; Copy init data
ldrcc r3, [r0], #4 ;--> LDRCC r2, [r0] + ADD r0, r0, #4
strcc r3, [r1], #4 ;--> STRCC r2, [r1] + ADD r1, r1, #4
bcc %B1
2
ldr pc,=On_The_Ram
On_The_Ram
;Copy and paste RW data/zero initialized data
ldr r0, =|Image$$RO$$Limit| ; Get pointer to ROM data
ldr r1, =|Image$$RW$$Base| ; and RAM copy
ldr r3, =|Image$$ZI$$Base|
;Zero init base => top of initialised data
cmp r0, r1 ; Check that they are different
beq %F2
1
cmp r1, r3 ; Copy init data
ldrcc r2, [r0], #4 ;--> LDRCC r2, [r0] + ADD r0, r0, #4
strcc r2, [r1], #4 ;--> STRCC r2, [r1] + ADD r1, r1, #4
bcc %B1
2
ldr r1, =|Image$$ZI$$Limit| ; Top of zero init segment
mov r2, #0
3
cmp r3, r1 ; Zero init
strcc r2, [r3], #4
bcc %B3
adrl r0, BootNand
adrl r1, BootNor
ldr r3,=BWSCON
ldr r3,[r3]
ands r3,r3,#0x06
movne r0,r1
bl PrintStr
adr r0,Say_Hello
bl PrintStr
bl __C_Inits
;sub lr,pc,#8
;ldr pc,=Main
bl Main ;Don't use main() because ......
b Auto_Reset
;function initializing stacks
InitStacks
;Don't use DRAM,such as stmfd,ldmfd......
;SVCstack is initialized before
;Under toolkit ver 2.5, 'msr cpsr,r1' can be used instead of 'msr cpsr_cxsf,r1'
mrs r0,cpsr
bic r0,r0,#MODEMASK
orr r1,r0,#UNDEFMODE|NOINT
msr cpsr_cxsf,r1 ;UndefMode
ldr sp,=UndefStack
orr r1,r0,#ABORTMODE|NOINT
msr cpsr_cxsf,r1 ;AbortMode
ldr sp,=AbortStack
orr r1,r0,#IRQMODE|NOINT
msr cpsr_cxsf,r1 ;IRQMode
ldr sp,=IRQStack
orr r1,r0,#FIQMODE|NOINT
msr cpsr_cxsf,r1 ;FIQMode
ldr sp,=FIQStack
bic r0,r0,#MODEMASK|NOINT
orr r1,r0,#SVCMODE
msr cpsr_cxsf,r1 ;SVCMode
ldr sp,=SVCStack
;USER mode has not be initialized.
mov pc,lr
;The LR register won't be valid if the current mode is not SVC mode.
EXPORT PrintChar
PrintChar
mov r1, #UART0_CTL_BASE
1
ldr r2, [r1, #oUTRSTAT]
;and r2, r2, #UTRSTAT_TX_EMPTY
tst r2, #UTRSTAT_TX_EMPTY
beq %B1
str r0, [r1, #oUTXHL]
mov pc, lr
PrintStr
stmfd sp!, {r4, lr}
movs r4, r0
ldmeqfd sp!, {r4, pc}
1
ldrb r0, [r4], #1
cmp r0, #0
ldmeqfd sp!, {r4, pc}
bl PrintChar
b %B1
; PrintHexNibble : prints the least-significant nibble in R0 as a
; hex digit
PrintHexNibble
adr r2, HEX_TO_ASCII_TABLE
and r0, r0, #0xF
ldr r0, [r2, r0] ; convert to ascii
b PrintChar
; PrintHexWord : prints the 4 bytes in R0 as 8 hex ascii characters
; followed by a newline
PrintHexWord
stmfd sp!, {r4, lr}
mov r4, r0
mov r0, r4, LSR #28
bl PrintHexNibble
mov r0, r4, LSR #24
bl PrintHexNibble
mov r0, r4, LSR #20
bl PrintHexNibble
mov r0, r4, LSR #16
bl PrintHexNibble
mov r0, r4, LSR #12
bl PrintHexNibble
mov r0, r4, LSR #8
bl PrintHexNibble
mov r0, r4, LSR #4
bl PrintHexNibble
mov r0, r4
bl PrintHexNibble
mov r0, #'\r'
bl PrintChar
mov r0, #'\n'
bl PrintChar
ldmfd sp!, {r4, pc}
ALIGN 4
HEX_TO_ASCII_TABLE
DCB "0123456789ABCDEF"
Say_Hello
DCB "Welcome to uCOS-II World.\r\n",0
BootNand
DCB "boot from NAND flash\r\n",0
BootNor
DCB "boot from NOR flash\r\n",0
ALIGN 4
SMRDATA
; Memory configuration should be optimized for best performance
; The following parameter is not optimized.
; Memory access cycle parameter strategy
; 1) The memory settings is safe parameters even at HCLK=75Mhz.
; 2) SDRAM refresh period is for HCLK=75Mhz.
DCD (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+(B6_BWSCON<<24)+(B7_BWSCON<<28))
DCD ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC)) ;GCS0
DCD ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC)) ;GCS1
DCD ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC)) ;GCS2
DCD ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC)) ;GCS3
DCD ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC)) ;GCS4
DCD ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC)) ;GCS5
DCD ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN)) ;GCS6
DCD ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN)) ;GCS7
DCD (0x008e04eb) ;DCD ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)
DCD 0xB2 ;SCLK power saving mode, BANKSIZE 128M/128M
DCD 0x20 ;MRSR6 CL=2clk
DCD 0x20 ;MRSR7
; Processor clock values
ALIGN 4
clock_locktime
DCD vLOCKTIME
mpll_value
DCD (M_MDIV<<12)+(M_PDIV<<4)+(M_SDIV)
clkdivn_value
DCD vCLKDIVN
; initial values for serial
;uart_ulcon
; DCD vULCON
;uart_ucon
; DCD vUCON
;uart_ufcon
; DCD vUFCON
;uart_umcon
; DCD vUMCON
SerBase
DCD UART0_CTL_BASE
; inital values for GPIO
gpio_con_uart
DCD vGPHCON
gpio_up_uart
DCD vGPHUP
AREA RamData, DATA, READWRITE
^ _INT_VIC_STARTADDRESS
HandleReset # 4
HandleUndef # 4
HandleSWI # 4
HandlePabort # 4
HandleDabort # 4
HandleReserved # 4
HandleIRQ # 4
HandleFIQ # 4
;Don't use the label 'IntVectorTable',
;The value of IntVectorTable is different with the address you think it may be.
;IntVectorTable
HandleEINT0 # 4
HandleEINT1 # 4
HandleEINT2 # 4
HandleEINT3 # 4
HandleEINT4_7 # 4
HandleEINT8_23 # 4
HandleRSV6 # 4
HandleBATFLT # 4
HandleTICK # 4
HandleWDT # 4
HandleTIMER0 # 4
HandleTIMER1 # 4
HandleTIMER2 # 4
HandleTIMER3 # 4
HandleTIMER4 # 4
HandleUART2 # 4
HandleLCD # 4
HandleDMA0 # 4
HandleDMA1 # 4
HandleDMA2 # 4
HandleDMA3 # 4
HandleMMC # 4
HandleSPI0 # 4
HandleUART1 # 4
HandleRSV24 # 4
HandleUSBD # 4
HandleUSBH # 4
HandleIIC # 4
HandleUART0 # 4
HandleSPI1 # 4
HandleRTC # 4
HandleADC # 4
END