www.pudn.com > S3C2440_uCos-II.rar > 2440addr.inc
;====================================================================
; File Name : 2440addr.a
; Function : S3C2440 Define Address Register (Assembly)
; Date : March 27, 2002
; Revision : Programming start (February 18,2002) -> SOP
; Revision : 03.11.2003 ver 0.0 Attatched for 2440
;====================================================================
GBLL BIG_ENDIAN__
BIG_ENDIAN__ SETL {FALSE}
;=================
; Memory control
;=================
BWSCON EQU 0x48000000 ;Bus width & wait status
BANKCON0 EQU 0x48000004 ;Boot ROM control
BANKCON1 EQU 0x48000008 ;BANK1 control
BANKCON2 EQU 0x4800000c ;BANK2 control
BANKCON3 EQU 0x48000010 ;BANK3 control
BANKCON4 EQU 0x48000014 ;BANK4 control
BANKCON5 EQU 0x48000018 ;BANK5 control
BANKCON6 EQU 0x4800001c ;BANK6 control
BANKCON7 EQU 0x48000020 ;BANK7 control
REFRESH EQU 0x48000024 ;DRAM/SDRAM refresh
BANKSIZE EQU 0x48000028 ;Flexible Bank Size
MRSRB6 EQU 0x4800002c ;Mode register set for SDRAM Bank6
MRSRB7 EQU 0x48000030 ;Mode register set for SDRAM Bank7
;==========================
; CLOCK & POWER MANAGEMENT
;==========================
LOCKTIME EQU 0x4c000000 ;PLL lock time counter
MPLLCON EQU 0x4c000004 ;MPLL Control
UPLLCON EQU 0x4c000008 ;UPLL Control
CLKCON EQU 0x4c00000c ;Clock generator control
CLKSLOW EQU 0x4c000010 ;Slow clock control
CLKDIVN EQU 0x4c000014 ;Clock divider control
CLK_CTL_BASE EQU 0x4C000000
;/* Offset */
oLOCKTIME EQU 0x00 ;/* R/W, PLL lock time count register */
oMPLLCON EQU 0x04 ;/* R/W, MPLL configuration register */
oUPLLCON EQU 0x08 ;/* R/W, UPLL configuration register */
oCLKCON EQU 0x0C ;/* R/W, Clock generator control reg. */
oCLKSLOW EQU 0x10 ;/* R/W, Slow clock control register */
oCLKDIVN EQU 0x14 ;/* R/W, Clock divider control */
;=================
; INTERRUPT
;=================
SRCPND EQU 0x4a000000 ;Interrupt request status
INTMOD EQU 0x4a000004 ;Interrupt mode control
INTMSK EQU 0x4a000008 ;Interrupt mask control
PRIORITY EQU 0x4a00000c ;IRQ priority control <-- May 06, 2002 SOP
INTPND EQU 0x4a000010 ;Interrupt request status
INTOFFSET EQU 0x4a000014 ;Interruot request source offset
SUSSRCPND EQU 0x4a000018 ;Sub source pending
INTSUBMSK EQU 0x4a00001c ;Interrupt sub mask
;/* NAND Flash Controller */
NAND_CTL_BASE EQU 0x4E000000
;/* Offset */
oNFCONF EQU 0x00
oNFCONT EQU 0x04
oNFCMD EQU 0x08
oNFADDR EQU 0x0c
oNFDATA EQU 0x10
oNFSTAT EQU 0x20
oNFECC EQU 0x2c
;=================
; UART
;=================
UART0_CTL_BASE EQU 0x50000000 ;UART 2 Receive buffer
oULCON EQU 0x00 ;/* R/W, UART line control register */
oUCON EQU 0x04 ;/* R/W, UART control register */
oUFCON EQU 0x08 ;/* R/W, UART FIFO control register */
oUMCON EQU 0x0C ;/* R/W, UART modem control register */
oUTRSTAT EQU 0x10 ;/* R , UART Tx/Rx status register */
oUERSTAT EQU 0x14 ;/* R , UART Rx error status register */
oUFSTAT EQU 0x18 ;/* R , UART FIFO status register */
oUMSTAT EQU 0x1C ;/* R , UART Modem status register */
oUTXHL EQU 0x20 ;/* W, UART transmit(little-end) buffer */
oUTXHB EQU 0x23 ;/* W, UART transmit(big-end) buffer */
oURXHL EQU 0x24 ;/* R , UART receive(little-end) buffer */
oURXHB EQU 0x27 ;/* R , UART receive(big-end) buffer */
oUBRDIV EQU 0x28 ;/* R/W, Baud rate divisor register */
;/* ... */
UTRSTAT_TX_EMPTY EQU (1 << 2)
UTRSTAT_RX_READY EQU (1 << 0)
UART_ERR_MASK EQU 0xF
;/* GPIO */
GPIO_CTL_BASE EQU 0x56000000
;/* Offset */
oGPIO_CON EQU 0x0 ;/* R/W, Configures the pins of the port */
oGPIO_DAT EQU 0x4 ;/* R/W, Data register for port */
oGPIO_UP EQU 0x8 ;/* R/W, Pull-up disable register */
oGPIO_RESERVED EQU 0xC ;/* R/W, Reserved */
oGPIO_A EQU 0x00
oGPIO_B EQU 0x10
oGPIO_C EQU 0x20
oGPIO_D EQU 0x30
oGPIO_E EQU 0x40
oGPIO_F EQU 0x50
oGPIO_G EQU 0x60
oGPIO_H EQU 0x70
oMISCCR EQU 0x80 ;/* R/W, Miscellaneous control register */
oDCLKCON EQU 0x84 ;/* R/W, DCLK0/1 control register */
oEXTINT0 EQU 0x88 ;/* R/W, External interrupt control reg. 0 */
oEXTINT1 EQU 0x8C ;/* R/W, External interrupt control reg. 1 */
oEXTINT2 EQU 0x90 ;/* R/W, External interrupt control reg. 2 */
oEINTFLT0 EQU 0x94 ;/* R/W, Reserved */
oEINTFLT1 EQU 0x98 ;/* R/W, Reserved */
oEINTFLT2 EQU 0x9C ;/* R/W, External interrupt control reg. 2 */
oEINTFLT3 EQU 0xA0 ;/* R/W, External interrupt control reg. 3 */
oEINTMASK EQU 0xA4 ;/* R/W, External interrupt mask register */
oEINTPEND EQU 0xA8 ;/* R/W, External interrupt pending reg. */
;=================
; I/O PORT for LED
;=================
GPFCON EQU 0x56000050 ;Port F control
GPFDAT EQU 0x56000054 ;Port F data
GPFUP EQU 0x56000058 ;Pull-up control F
;Miscellaneous register
MISCCR EQU 0x56000080 ;Miscellaneous control
DCKCON EQU 0x56000084 ;DCLK0/1 control
EXTINT0 EQU 0x56000088 ;External interrupt control register 0
EXTINT1 EQU 0x5600008c ;External interrupt control register 1
EXTINT2 EQU 0x56000090 ;External interrupt control register 2
EINTFLT0 EQU 0x56000094 ;Reserved
EINTFLT1 EQU 0x56000098 ;Reserved
EINTFLT2 EQU 0x5600009c ;External interrupt filter control register 2
EINTFLT3 EQU 0x560000a0 ;External interrupt filter control register 3
EINTMASK EQU 0x560000a4 ;External interrupt mask
EINTPEND EQU 0x560000a8 ;External interrupt pending
GSTATUS0 EQU 0x560000ac ;External pin status
GSTATUS1 EQU 0x560000b0 ;Chip ID(0x32440000)
GSTATUS2 EQU 0x560000b4 ;Reset type
GSTATUS3 EQU 0x560000b8 ;Saved data0(32-bit) before entering POWER_OFF mode
GSTATUS4 EQU 0x560000bc ;Saved data1(32-bit) before entering POWER_OFF mode
;Added for 2440 ; DonGo
MSLCON EQU 0x560000cc ;Memory sleep control register
;=================
; LCD CONTROLLER
;=================
LCDCON1 EQU 0x4d000000 ;LCD control 1
LCDCON2 EQU 0x4d000004 ;LCD control 2
LCDCON3 EQU 0x4d000008 ;LCD control 3
LCDCON4 EQU 0x4d00000c ;LCD control 4
LCDCON5 EQU 0x4d000010 ;LCD control 5
LCDSADDR1 EQU 0x4d000014 ;STN/TFT Frame buffer start address 1
LCDSADDR2 EQU 0x4d000018 ;STN/TFT Frame buffer start address 2
LCDSADDR3 EQU 0x4d00001c ;STN/TFT Virtual screen address set
REDLUT EQU 0x4d000020 ;STN Red lookup table
GREENLUT EQU 0x4d000024 ;STN Green lookup table
BLUELUT EQU 0x4d000028 ;STN Blue lookup table
DITHMODE EQU 0x4d00004c ;STN Dithering mode
TPAL EQU 0x4d000050 ;TFT Temporary palette
LCDINTPND EQU 0x4d000054 ;LCD Interrupt pending
LCDSRCPND EQU 0x4d000058 ;LCD Interrupt source
LCDINTMSK EQU 0x4d00005c ;LCD Interrupt mask
LPCSEL EQU 0x4d000060 ;LPC3600 Control
;=================
; WATCH DOG TIMER
;=================
WTCON EQU 0x53000000 ;Watch-dog timer mode
WTDAT EQU 0x53000004 ;Watch-dog timer data
WTCNT EQU 0x53000008 ;Eatch-dog timer count
END