www.pudn.com > DMBDRV.rar > PxaRegs.h
#ifndef __PXA27XREGS_H__
#define __PXA27XREGS_H__
#include "pxa_ssp.h"
//#include "xllp_gpio_plat.h"
#include "xllp_defs.h"
#ifdef PXA27x
#define OST_OFFSET 0x00A00000 // OS Timer
#define GPIO_OFFSET 0x00E00000 // GPIO
#define SSP1_OFFSET 0x01000000 // SSP 1
#define CLK_OFFSET 0x01300000 // Clock Manager
#define SSP2_OFFSET 0x01700000 // SSP 2
#define SSP3_OFFSET 0x01900000 // SSP 3
#else
#ifdef PXA31x
#define OST_OFFSET 0x00A00000 // OS Timer
#define GPIO_OFFSET 0x00E00000 // GPIO
#define MFPR_OFFSET 0x00E10000 //MFPR
#define CLK_OFFSET 0x01300000 // Clock Manager
#define SSP1_OFFSET 0x01000000 // SSP 1
#define SSP2_OFFSET 0x01700000 // SSP 2
#define SSP3_OFFSET 0x01900000 // SSP 3
#define SSP4_OFFSET 0x01A00000 // SSP 3
#endif /*PXA31x*/
#endif /*PXA27x*/
#define PERIF_BASE_PHYSICAL 0x40000000
#define GPIO_BASE_PHYSICAL (PERIF_BASE_PHYSICAL + GPIO_OFFSET)
#define MFPR_BASE_PHYSICAL (PERIF_BASE_PHYSICAL + MFPR_OFFSET)
#define MFPR_MEMORY_SPACE 0x10000
#define OST_BASE_PHYSICAL (PERIF_BASE_PHYSICAL + OST_OFFSET)
#define SSP1_BASE_PHYSICAL (PERIF_BASE_PHYSICAL + SSP1_OFFSET)
#define SSP2_BASE_PHYSICAL (PERIF_BASE_PHYSICAL + SSP2_OFFSET)
#define SSP3_BASE_PHYSICAL (PERIF_BASE_PHYSICAL + SSP3_OFFSET)
#define SSP4_BASE_PHYSICAL (PERIF_BASE_PHYSICAL + SSP4_OFFSET)
#define CLK_BASE_PHYSICAL (PERIF_BASE_PHYSICAL + CLK_OFFSET)
#ifdef PXA27x
#define XLLP_GPIO_BIT_SSP2CLK_GADR1 (0x1<<4)
#define XLLP_GPIO_BIT_SSP2FRM_GADR1 (0x1<<5)
#define XLLP_GPIO_BIT_SSP2TXD_GADR1 (0x1<<6)
#define XLLP_GPIO_BIT_SSP2RXD_GADR1 (0x1<<8)
//GAFR (alternate function) CONFIGURATION
#define XLLP_GPIO_AF2_SSP2CLK_GAFR1_L (0x2<<8)//alt func 2
#define XLLP_GPIO_AF2_SSP2CLK_MASK_GAFR1_L (0x3<<8)
#define XLLP_GPIO_AF2_SSP2FRM_GAFR1_L (0x2<<10)//alt func 2
#define XLLP_GPIO_AF2_SSP2FRM_MASK_GAFR1_L (0x3<<10)
#define XLLP_GPIO_AF2_SSP2TXD_GAFR1_L (0x2<<12)//alt func 2
#define XLLP_GPIO_AF2_SSP2TXD_MASK_GAFR1_L (0x3<<12)
#define XLLP_GPIO_AF1_SSP2RXD_GAFR1_L (0x1<<16)//alt func 1
#define XLLP_GPIO_AF1_SSP2RXD_MASK_GAFR1_L (0x3<<16)
#else
#ifdef PXA31x
/*Bit definitions for MFPR*/
#define FAST1MA (0 << 10)
#define FAST2MA (1 << 10)
#define FAST3MA (2 << 10)
#define FAST4MA (3 << 10)
#define SLOW6MA (4 << 10)
#define FAST6MA (5 << 10)
#define SLOW10MA (6 << 10)
#define FAST10MA (7 << 10)
#define AF0 0
#define AF1 1
#define AF2 2
#define AF3 3
#define AF4 4
#define AF5 5
#define AF6 6
#define AF7 7
#define SSP1_MFPR_TX 316
#define SSP1_MFPR_RX 317
#define SSP1_MFPR_CLK 319
#define SSP1_MFPR_FRM 315
/*Set the AF coresponding with these GPIO pins*/
#define SSP1_AF AF1
#define SSP1_GPDR_TX GPDR2
#define SSP1_GPDR_RX GPDR2
#define SSP1_GPDR_CLK GPDR2
#define SSP1_GPDR_FRM GPDR2
#define XLLP_GPIO_BIT_SSP1_TXD (0x1<<23)
#define XLLP_GPIO_BIT_SSP1_RXD (0x1<<24)
#define XLLP_GPIO_BIT_SSP1_CLK (0x1<<26)
#define XLLP_GPIO_BIT_SSP1_FRM (0x1<<22)
#define SSP2_MFPR_TX 256
#define SSP2_MFPR_RX 257
#define SSP2_MFPR_CLK 254
#define SSP2_MFPR_FRM 255
/*Set the AF coresponding with these GPIO pins*/
#define SSP2_AF AF2
#define SSP2_GPDR_TX GPDR0
#define SSP2_GPDR_RX GPDR0
#define SSP2_GPDR_CLK GPDR0
#define SSP2_GPDR_FRM GPDR0
#define XLLP_GPIO_BIT_SSP2TXD (0x1<<27)
#define XLLP_GPIO_BIT_SSP2RXD (0x1<<28)
#define XLLP_GPIO_BIT_SSP2CLK (0x1<<25)
#define XLLP_GPIO_BIT_SSP2FRM (0x1<<26)
#define SSP3_MFPR_TX 322
#define SSP3_MFPR_RX 323
#define SSP3_MFPR_CLK 320
#define SSP3_MFPR_FRM 321
/*Set the AF coresponding with these GPIO pins*/
#define SSP3_AF AF1
#define SSP3_GPDR_TX GPDR2
#define SSP3_GPDR_RX GPDR2
#define SSP3_GPDR_CLK GPDR2
#define SSP3_GPDR_FRM GPDR2
#define XLLP_GPIO_BIT_SSP3TXD (0x1<<29)
#define XLLP_GPIO_BIT_SSP3RXD (0x1<<30)
#define XLLP_GPIO_BIT_SSP3CLK (0x1<<27)
#define XLLP_GPIO_BIT_SSP3FRM (0x1<<28)
#define SSP4_MFPR_TX 329
#define SSP4_MFPR_RX 330
#define SSP4_MFPR_CLK 327
#define SSP4_MFPR_FRM 328
/*Set the AF coresponding with these GPIO pins*/
#define SSP4_AF AF1
#define SSP4_GPDR_TX GPDR3
#define SSP4_GPDR_RX GPDR3
#define SSP4_GPDR_CLK GPDR2
#define SSP4_GPDR_FRM GPDR3
#define XLLP_GPIO_BIT_SSP4TXD (0x1<<1)
#define XLLP_GPIO_BIT_SSP4RXD (0x1<<2)
#define XLLP_GPIO_BIT_SSP4CLK (0x1<<31)
#define XLLP_GPIO_BIT_SSP4FRM (0x1<<0)
#endif /*PXA31x*/
#endif /*PXA27x*/
//
// Clock Manager (CLKMGR) Register Bank
//
#ifdef PXA270
typedef struct
{
XLLP_VUINT32_T cccr; // Core Clock Configuration register
XLLP_VUINT32_T cken; // Clock Enable register
XLLP_VUINT32_T oscc; // Oscillator Configuration register
XLLP_VUINT32_T ccsr; // Core Clock Status register
} XLLP_CLKMGR_T, *P_XLLP_CLKMGR_T;
#define SSP_CLK_ENABLE (v_pClkRegs->cken)
#define XLLP_CLKEN_SSP1 (0x1u << 23)
#define XLLP_CLKEN_SSP2 (0x1u << 3)
#define XLLP_CLKEN_SSP3 (0x1u << 4)
#else
#ifdef PXA31x
typedef struct
{
XLLP_VUINT32_T accr;
XLLP_VUINT32_T acsr;
XLLP_VUINT32_T aicsr;
XLLP_VUINT32_T d0cken_a;
XLLP_VUINT32_T d0cken_b;
XLLP_VUINT32_T ac97_div;
}XLLP_APP_CLOCKMGR_T, *P_XLLP_APP_CLOCKMGR_T;
#define SSP_CLK_ENABLE (v_pClkRegs->d0cken_a)
#define XLLP_CLKEN_SSP1 (0x1u << 26)
#define XLLP_CLKEN_SSP2 (0x1u << 27)
#define XLLP_CLKEN_SSP3 (0x1u << 28)
#define XLLP_CLKEN_SSP4 (0x1u << 29)
#endif /*PXA31x*/
#endif /*PXA27x*/
// SSP controller registers
/*
* SSP Serial Port Registers
* PXA250, PXA255, PXA26x and PXA27x SSP controllers are all slightly different.
* PXA255, PXA26x and PXA27x have extra ports, registers and bits.
*/
/* Common PXA2xx bits first */
#define SSCR0_DSS (0x0000000f) /* Data Size Select (mask) */
#define SSCR0_DataSize(x) ((x) - 1) /* Data Size Select [4..16] */
#define SSCR0_FRF (0x00000030) /* FRame Format (mask) */
#define SSCR0_Motorola (0x0 << 4) /* Motorola's Serial Peripheral Interface (SPI) */
#define SSCR0_TI (0x1 << 4) /* Texas Instruments' Synchronous Serial Protocol (SSP) */
#define SSCR0_National (0x2 << 4) /* National Microwire */
#define SSCR0_ECS (1 << 6) /* External clock select */
#define SSCR0_SSE (1 << 7) /* Synchronous Serial Port Enable */
#define SSCR0_SCR (0x0000ff00) /* Serial Clock Rate (mask) */
#define SSCR0_SerClkDiv(x) ((((x) - 2)/2) << 8) /* Divisor [2..512] */
#define SSCR1_RIE (1 << 0) /* Receive FIFO Interrupt Enable */
#define SSCR1_TIE (1 << 1) /* Transmit FIFO Interrupt Enable */
#define SSCR1_LBM (1 << 2) /* Loop-Back Mode */
#define SSCR1_SPO (1 << 3) /* Motorola SPI SSPSCLK polarity setting */
#define SSCR1_SPH (1 << 4) /* Motorola SPI SSPSCLK phase setting */
#define SSCR1_MWDS (1 << 5) /* Microwire Transmit Data Size */
#define SSCR1_TFT (0x000003c0) /* Transmit FIFO Threshold (mask) */
#define SSCR1_TxTresh(x) (((x) - 1) << 6) /* level [1..16] */
#define SSCR1_RFT (0x00003c00) /* Receive FIFO Threshold (mask) */
#define SSCR1_RxTresh(x) (((x) - 1) << 10) /* level [1..16] */
#define SSSR_TNF (1 << 2) /* Transmit FIFO Not Full */
#define SSSR_RNE (1 << 3) /* Receive FIFO Not Empty */
#define SSSR_BSY (1 << 4) /* SSP Busy */
#define SSSR_TFS (1 << 5) /* Transmit FIFO Service Request */
#define SSSR_RFS (1 << 6) /* Receive FIFO Service Request */
#define SSSR_ROR (1 << 7) /* Receive FIFO Overrun */
#define SSCR0_TIM (1 << 23) /* Transmit FIFO Under Run Interrupt Mask */
#define SSCR0_RIM (1 << 22) /* Receive FIFO Over Run interrupt Mask */
#define SSCR0_NCS (1 << 21) /* Network Clock Select */
#define SSCR0_EDSS (1 << 20) /* Extended Data Size Select */
/* extra bits in PXA255, PXA26x and PXA27x SSP ports */
#define SSCR0_PSP (3 << 4) /* PSP - Programmable Serial Protocol */
#define SSCR1_TTELP (1 << 31) /* TXD Tristate Enable Last Phase */
#define SSCR1_TTE (1 << 30) /* TXD Tristate Enable */
#define SSCR1_EBCEI (1 << 29) /* Enable Bit Count Error interrupt */
#define SSCR1_SCFR (1 << 28) /* Slave Clock free Running */
#define SSCR1_ECRA (1 << 27) /* Enable Clock Request A */
#define SSCR1_ECRB (1 << 26) /* Enable Clock request B */
#define SSCR1_SCLKDIR (1 << 25) /* Serial Bit Rate Clock Direction */
#define SSCR1_SFRMDIR (1 << 24) /* Frame Direction */
#define SSCR1_RWOT (1 << 23) /* Receive Without Transmit */
#define SSCR1_TRAIL (1 << 22) /* Trailing Byte */
#define SSCR1_TSRE (1 << 21) /* Transmit Service Request Enable */
#define SSCR1_RSRE (1 << 20) /* Receive Service Request Enable */
#define SSCR1_TINTE (1 << 19) /* Receiver Time-out Interrupt enable */
#define SSCR1_PINTE (1 << 18) /* Peripheral Trailing Byte Interupt Enable */
#define SSCR1_STRF (1 << 15) /* Select FIFO or EFWR */
#define SSCR1_EFWR (1 << 14) /* Enable FIFO Write/Read */
#define SSSR_BCE (1 << 23) /* Bit Count Error */
#define SSSR_CSS (1 << 22) /* Clock Synchronisation Status */
#define SSSR_TUR (1 << 21) /* Transmit FIFO Under Run */
#define SSSR_EOC (1 << 20) /* End Of Chain */
#define SSSR_TINT (1 << 19) /* Receiver Time-out Interrupt */
#define SSSR_PINT (1 << 18) /* Peripheral Trailing Byte Interrupt */
#define SSPSP_DMYSTOP(x) (x << 23) /* Dummy Stop */
#define SSPSP_SFRMWDTH(x) (x << 16) /* Serial Frame Width */
#define SSPSP_SFRMDLY(x) (x << 9) /* Serial Frame Delay */
#define SSPSP_DMYSTRT(x) (x << 7) /* Dummy Start */
#define SSPSP_STRTDLY(x) (x << 4) /* Start Delay */
#define SSPSP_ETDS (1 << 3) /* End of Transfer data State */
#define SSPSP_SFRMP (1 << 2) /* Serial Frame Polarity */
#define SSPSP_SCMODE(x) (x << 0) /* Serial Bit Rate Clock Mode */
#define XLLP_SSCR0_SSE (0x1<<7) // 1 -- SSP operation is enabled
#endif /*__PXA27XREGS_H__*/