www.pudn.com > DMBDRV.rar > PxaDMA.h
#ifndef _DMADRIVER_H #define _DMADRIVER_H #include#include "DmaCedebug.h" #include "CEDDK.h" #define ALIGNMENT_MASK (PAGE_SIZE-1) #define PAGE_MASK (PAGE_SIZE-1) #define MAX_WAIT_LOOP 0x10000 #define DMAC_OFFSET 0x0 #define PERIF_BASE_C_VIRTUAL 0x84500000 #define CACHED_TO_UNCACHED_OFFSET 0x20000000 #define PERIF_BASE_PHYSICAL 0x40000000 #define DMAC_BASE_PHYSICAL (PERIF_BASE_PHYSICAL + DMAC_OFFSET) #define PERIF_BASE_U_VIRTUAL (PERIF_BASE_C_VIRTUAL+CACHED_TO_UNCACHED_OFFSET) #define DMAC_BASE_U_VIRTUAL (PERIF_BASE_U_VIRTUAL + DMAC_OFFSET) #define DMAC_BASE_ADDRESS (int)pDmacAddr // // MEMC // #define MEMC_BASE_ADDRESS (int)pMemcArrdess #define GPIO_OFFSET 0x00E00000 #define GPIO_BASE_U_VIRTUAL (PERIF_BASE_U_VIRTUAL + GPIO_OFFSET) #define GPIO_BASE_ADDRESS (int)pGpioArrdess #define FPGA_REGS_BASE_PHYSICAL 0x08000000 #define FPGA_REGS_BASE_C_VIRTUAL 0x96B00000 #define FPGA_REGS_BASE_U_VIRTUAL (FPGA_REGS_BASE_C_VIRTUAL + CACHED_TO_UNCACHED_OFFSET) #define FPGA_BASE_ADDRESS (int)pFpgaArrdess #define PWR_OFFSET 0x00F00000 #define PWR_BASE_PHYSICAL (PERIF_BASE_PHYSICAL + PWR_OFFSET) #define PWR_BASE_C_VIRTUAL (PERIF_BASE_C_VIRTUAL + PWR_OFFSET) #define PWR_BASE_U_VIRTUAL (PERIF_BASE_U_VIRTUAL + PWR_OFFSET) #define MEMC_BASE_PHYSICAL 0x48000000 #define MEMC_BASE_C_VIRTUAL 0x84300000 #define MEMC_BASE_U_VIRTUAL (MEMC_BASE_C_VIRTUAL+CACHED_TO_UNCACHED_OFFSET) #define PWR_BASE_ADDRESS (int)pPwrArrdess /** * Used in DMA handler definition **/ #define DMAC_CHANNEL_NUM 32 #define DMAC_DRCMR1_NUM 64 #define DMAC_DRCMR2_NUM 11 #define DMA_CHANNEL 0 /* Bit Definitions of drcrm register*/ #define DMAC_DRCRM_MAP_CHANNEL (1U<<7) /* Bit Definitions of dcsr register*/ #define DMAC_DCSR_BUSERRINTR (1U) #define DMAC_DCSR_STARTINTR (1U<<1) #define DMAC_DCSR_ENDINTR (1U<<2) #define DMAC_DCSR_STOPINTR (1U<<3) #define DMAC_DCSR_RASINTR (1U<<4) #define DMAC_DCSR_EORINT (1U<<9) #define DMAC_DCSR_EORIRQEN (1U<<28) #define DMAC_DCSR_NODESCFETCH (1U<<30) #define DMAC_DCSR_RUN (1U<<31) /* Bit Dfinitions od DCMD register*/ #define DMAC_DCMD_INCSRCADDR (1U<<31) #define DMAC_DCMD_INCTRGADDR (1U<<30) #define DMAC_DCMD_FLOWSRC (1U<<29) #define DMAC_DCMD_FLOWTRG (1U<<28) #define DMAC_DCMD_ENDIRQEN (1U<<21) #define DMAC_DCMD_BURST_16 (2U<<16) #define DMAC_DCMD_BURST_32 (3U<<16) #define DMAC_DCMD_WIDTH_16 (2U<<14) #define DMAC_DCMD_WIDTH_32 (3U<<14) #define DMAC_DCSR_CLEAR_ALL_INTERRUPTS (DMAC_DCSR_BUSERRINTR | DMAC_DCSR_STARTINTR | \ DMAC_DCSR_ENDINTR | DMAC_DCSR_STOPINTR | DMAC_DCSR_RASINTR) typedef struct DMAC_FRAME_DESCRIPTOR_S { unsigned int ddadr; // address of the next frame descriptor (physical address) unsigned int dsadr; // address of the source data (physical address) unsigned int dtadr; // address of the destination unsigned int dcmd; // dma command }DMAC_FRAME_DESCRIPTOR_ST; typedef struct { DWORD dcsr[DMAC_CHANNEL_NUM]; /* DMA Control/Status Registers 0-31 */ DWORD reserved0[0x8]; /* RESERVED0 */ DWORD dalgn; /* DMA Alignment Register 31 */ DWORD reserved1[0xF]; /* RESERVED0 */ DWORD drqsr0; /* DMA DREQ(0) Status Register */ DWORD drqsr1; /* DMA DREQ(1) Status Register */ DWORD reserved2[0x2]; /* RESERVED1 */ DWORD dint; /* DMA Interrupt Register */ DWORD reserved3[0x3]; /* RESERVED2 */ DWORD drcmr1[DMAC_DRCMR1_NUM]; /* Request to Channel Map for DREQ 0-63 */ DMAC_FRAME_DESCRIPTOR_ST ddg[DMAC_CHANNEL_NUM]; /* DMA Desc Group for channel 0-31 */ DWORD reserved4[0x340]; /* RESERVED3 */ DWORD drcmr2[DMAC_DRCMR2_NUM]; /* Request to Channel Map 64-67 */ } DMAC_REGISTERS, *DMAC_REGISTERS_P; #define XLLP_BIT_8 ( 1u << 8 ) #define XLLP_BIT_9 ( 1u << 9 ) #define XLLP_BIT_20 ( 1u << 20 ) #define XLLP_GPIO_BIT_MBREQ ( XLLP_BIT_20 ) typedef struct{ volatile unsigned long rsvd0[4]; // 0800_0000 -> 0800_000F volatile unsigned long hex_led; // 0800_0010 -> 0800_0013 volatile unsigned long hex_led2; // 0800_0014 -> 0800_0017 volatile unsigned long rsvd1[10]; // 0800_0018 -> 0800_003F volatile unsigned long disc_blnk_led; // 0800_0040 -> 0800_0043 volatile unsigned long rsvd2[7]; // 0800_0044 -> 0800_005F volatile unsigned long gpsw; // 0800_0060 -> 0800_0063 volatile unsigned long rsvd3[7]; // 0800_0064 -> 0080_007F volatile unsigned long misc_wr; // 0800_0080 -> 0080_0083 volatile unsigned long misc_wr2; // 0800_0084 -> 0080_0087 volatile unsigned long rsvd4[2]; // 0800_0088 -> 0800_008F volatile unsigned long misc_rd; // 0800_0090 -> 0800_0093 volatile unsigned long rsvd5[11]; // 0800_0094 -> 0800_00BF volatile unsigned long int_msk_en; // 0800_00C0 -> 0800_00C3 volatile unsigned long rsvd6[3]; // 0800_00C4 -> 0800_00CF volatile unsigned long int_set_clr; // 0800_00D0 -> 0800_00D3 volatile unsigned long rsvd7[3]; // 0800_00D4 -> 0800_00DF volatile unsigned long pcmcia0_srcr; // 0800_00E0 -> 0800_00E3 volatile unsigned long pcmcia1_srcr; // 0800_00E4 -> 0800_00E7 }FPGA_REGISTERS, *FPGA_REGISTERS_P; #define EXPBD_IRQ_MASK (0x1 << 7) /** GPIO Register Definitions **/ /* Bit definition for GAFRx register */ #define GPIO_GAFR_PORTS_IN_REG 16 #define GPIO_GPDR_PORTS_IN_REG 32 #define GPIO_GPLR_PORTS_IN_REG 32 #define GPIO_GAFR_BITS_PER_CHANNEL 2 #define GPIOC_GAFRX_AFX_GPIO 0 #define GPIOC_GAFRX_AFX_FUNC1 1 #define GPIOC_GAFRX_AFX_FUNC2 2 #define GPIOC_GAFRX_AFX_FUNC3 3 #define GPIO_DREQ0_PORT 20 #define GPIO_DREQ0_FUNCTION GPIOC_GAFRX_AFX_FUNC1 #define GPIO_DREQ1_PORT 80 #define GPIO_DREQ1_FUNCTION GPIOC_GAFRX_AFX_FUNC1 #define GPIO_DREQ2_PORT 85 #define GPIO_DREQ2_FUNCTION GPIOC_GAFRX_AFX_FUNC2 /* Bit Definitions for gpio detect 0 registers*/ #define GPIOC_GPXX_PIN_20 (1<<20) typedef struct { DWORD gplr0; /* Level Detect Reg. Bank 0 */ DWORD gplr1; /* Level Detect Reg. Bank 1 */ DWORD gplr2; /* Level Detect Reg. Bank 2 */ DWORD gpdr0; /* Data Direction Reg. Bank 0 */ DWORD gpdr1; /* Data Direction Reg. Bank 1 */ DWORD gpdr2; /* Data Direction Reg. Bank 2 */ DWORD gpsr0; /* Pin Output Set Reg. Bank 0 */ DWORD gpsr1; /* Pin Output Set Reg. Bank 1 */ DWORD gpsr2; /* Pin Output Set Reg. Bank 2 */ DWORD gpcr0; /* Pin Output Clr Reg. Bank 0 */ DWORD gpcr1; /* Pin Output Clr Reg. Bank 1 */ DWORD gpcr2; /* Pin Output Clr Reg. Bank 2 */ DWORD grer0; /* Ris. Edge Detect Enable Reg. Bank 0 */ DWORD grer1; /* Ris. Edge Detect Enable Reg. Bank 1 */ DWORD grer2; /* Ris. Edge Detect Enable Reg. Bank 2 */ DWORD gfer0; /* Fal. Edge Detect Enable Reg. Bank 0 */ DWORD gfer1; /* Fal. Edge Detect Enable Reg. Bank 1 */ DWORD gfer2; /* Fal. Edge Detect Enable Reg. Bank 2 */ DWORD gedr0; /* Edge Detect Status Reg. Bank 0 */ DWORD gedr1; /* Edge Detect Status Reg. Bank 1 */ DWORD gedr2; /* Edge Detect Status Reg. Bank 2 */ DWORD gafr0_l; /* Alt. Function Select Reg.[ 0:15 ] */ DWORD gafr0_u; /* Alt. Function Select Reg.[ 16:31 ] */ DWORD gafr1_l; /* Alt. Function Select Reg.[ 32:47 ] */ DWORD gafr1_u; /* Alt. Function Select Reg.[ 48:63 ] */ DWORD gafr2_l; /* Alt. Function Select Reg.[ 64:79 ] */ DWORD gafr2_u; /* Alt. Function Select Reg.[ 80:95 ] */ DWORD gafr3_l; /* Alt. Function Select Reg.[ 96:111] */ DWORD gafr3_u; /* Alt. Function Select Reg.[112:120] */ DWORD reserved1[35]; /* addr. offset 0x074-0x0fc */ DWORD GPLR3; /* Level Detect Reg. Bank 3 */ DWORD RESERVED2[2]; /* addr. offset 0x104-0x108 */ DWORD GPDR3; /* Data Direction Reg. Bank 3 */ DWORD RESERVED3[2]; /* addr. offset 0x110-0x114 */ DWORD GPSR3; /* Pin Output Set Reg. Bank 3 */ DWORD RESERVED4[2]; /* addr. offset 0x11c-0x120 */ DWORD GPCR3; /* Pin Output Clr Reg. Bank 3 */ DWORD RESERVED5[2]; /* addr. offset 0x128-0x12c */ DWORD GRER3; /* Ris. Edge Detect Enable Reg. Bank 3 */ DWORD RESERVED6[2]; /* addr. offset 0x134-0x138 */ DWORD GFER3; /* Fal. Edge Detect Enable Reg. Bank 3 */ DWORD RESERVED7[2]; /* addr. offset 0x140-0x144 */ DWORD GEDR3; /* Edge Detect Status Reg. Bank 3 */ } GPIO_REGISTERS, *GPIO_REGISTERS_P; typedef struct { DWORD noOfDesc; DWORD currentDesc; DMAC_FRAME_DESCRIPTOR_ST* desc; PHYSICAL_ADDRESS descPhyAddr; }DMA_TRANSACTION_PARAMS, *DMA_TRANSACTION_PARAMS_P; #endif /*_DMADRIVER_H*/