www.pudn.com > system.rar > init.asm
;******************************************************************************
; TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION
;
; Property of Texas Instruments -- For Unrestricted Internal Use Only
; Unauthorized reproduction and/or distribution is strictly prohibited. This
; product is protected under copyright law and trade secret law as an
; unpublished work. Created 1987, (C) Copyright 1996 Texas Instruments. All
; rights reserved.
;
;
; Filename : init.asm
;
; Description : Environment configuration
;
; Project : drivers
;
; Author : pmonteil@tif.ti.com Patrice Monteil.
;
; Version number : 1.4
;
; Date and time : 03/06/01 10:44:19
;
; Previous delta : 12/19/00 14:28:47
;
; SCCS file : /db/gsm_asp/db_ht96/dsp_0/gsw/rel_0/mcu_l1/release_gprs/mod/emu_p/EMU_P_C_SAMPLE_REQ1145_BIS/drivers1/board_7/SCCS/s.init.asm
;
; Sccs Id (SID) : '@(#) init.asm 1.4 03/06/01 10:44:19 '
;
;
;*****************************************************************************
; use in int.s for first initializations
.if BOARD = 6
.if CHIPSET != 12
CS0_MEM_REG .short 0x2A0 ;ROM init : 0 WS, 16 bits, little
CS1_MEM_REG .short 0x281 ;RAM init : 1 WS, 8 bits, little
CS2_MEM_REG .short 0x2A1 ;RAM init : 1 WS, 16 bits, little
CS3_MEM_REG .short 0x283 ;RAM init : 5 WS, 8 bits, little
CS4_MEM_REG .short 0xe85 ;RAM init : 5 WS, 8 bits, little
.endif
.if CHIPSET = 3
CS6_MEM_REG .short 0x0C0 ;Internal RAM init : 0 WS, 32 bits, little, write enable
.elseif CHIPSET = 4
CS6_MEM_REG .short 0x0C0 ;Internal RAM init : 0 WS, 32 bits, little, write enable
CS7_MEM_REG .short 0x0C0 ;Internal RAM init : 0 WS, 32 bits, little, write enable
.elseif CHIPSET = 5
CS6_MEM_REG .short 0x0C0 ;Internal RAM init : 0 WS, 32 bits, little, write enable
.elseif CHIPSET = 6
CS6_MEM_REG .short 0x0C0 ;Internal RAM init : 0 WS, 32 bits, little, write enable
.elseif CHIPSET = 7 | CHIPSET = 8
CS6_MEM_REG .short 0x0C0 ;Internal RAM init : 0 WS, 32 bits, little, write enable
CS7_MEM_REG .short 0x040 ;Internal BOOT ROM init : 0 WS, 32 bits, little, write disable
.elseif CHIPSET = 10
CS6_MEM_REG .short 0x0C0 ;Internal RAM init : 0 WS, 32 bits, little, write enable
CS7_MEM_REG .short 0x040 ;Internal BOOT ROM init : 0 WS, 32 bits, little, write disable
.elseif CHIPSET = 11
.if OP_L1_STANDALONE = 0
CS6_MEM_REG .short 0x0C0 ;Internal RAM init : 0 WS, 32 bits, little, write enable
CS7_MEM_REG .short 0x040 ;Internal BOOT ROM init : 0 WS, 32 bits, little, write disable
.endif
.elseif CHIPSET = 12
CS0_MEM_REG .short 0x2A1 ;RAM init : 1 WS, 16 bits, little
CS4_MEM_REG .short 0x2A1 ;RAM init : 1 WS, 16 bits, little
CS5_MEM_REG .short 0x2A1 ;ROM init : 0 WS, 16 bits, little
.endif ; CHIPSET = 3, 4, 5, 6, 7, 8, 10 or 11 or 12
.elseif BOARD = 7
.if OP_L1_STANDALONE = 1
.if CHIPSET = 6
CS0_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable
CS1_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable
.else
CS0_MEM_REG .short 0x2a0 ; 1 Dummy Cycle 16 bit 0 WS SW BP enable
CS1_MEM_REG .short 0x2a0 ; 1 Dummy Cycle 16 bit 0 WS SW BP enable
.endif ; CHIPSET = 6
.else ; OP_L1_STANDALONE
CS0_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable
.if OP_WCP = 1
CS1_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 0 WS SW BP enable
.else
CS1_MEM_REG .short 0x2a0 ; 1 Dummy Cycle 16 bit 0 WS SW BP enable
.endif
.endif ; OP_L1_STANDALONE
CS2_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable
CS3_MEM_REG .short 0x283 ; 1 Dummy Cycle 8 bit 3 WS SW BP enable
CS4_MEM_REG .short 0x281 ; 1 Dummy Cycle 8 bit 1 WS SW BP enable
.if CHIPSET = 3
CS6_MEM_REG .short 0x2c0 ; Internal RAM init : 0 WS, 32 bits, little, write enable
.elseif CHIPSET = 4
CS6_MEM_REG .short 0x0c0 ; Internal RAM init : 0 WS, 32 bits, little, write enable
CS7_MEM_REG .short 0x0c0 ; Internal RAM init : 0 WS, 32 bits, little, write enable
.elseif CHIPSET = 5
CS6_MEM_REG .short 0x0c0 ; Internal RAM init : 0 WS, 32 bits, little, write enable
.elseif CHIPSET = 6
.if OP_WCP = 1
CS6_MEM_REG .short 0x2c0 ; Internal RAM init : 0 WS, 32 bits, little, write enable
.else
CS6_MEM_REG .short 0x0c0 ; Internal RAM init : 0 WS, 32 bits, little, write enable
.endif
.elseif CHIPSET = 7 | CHIPSET = 8
.if OP_L1_STANDALONE = 1
CS6_MEM_REG .short 0x0c0 ; Internal RAM init : 0 WS, 32 bits, little, write enable
CS7_MEM_REG .short 0x040 ; Internal BOOT ROM init : 0 WS, 32 bits, little, write disable
.endif ; OP_L1_STANDALONE = 1
.elseif CHIPSET = 10
.if OP_L1_STANDALONE = 1
CS6_MEM_REG .short 0x0c0 ; Internal RAM init : 0 WS, 32 bits, little, write enable
CS7_MEM_REG .short 0x040 ; Internal BOOT ROM init : 0 WS, 32 bits, little, write disable
.endif ; OP_L1_STANDALONE = 1
.endif ; CHIPSET = 3, 4, 5, 6, 7, 8 or 10
.elseif BOARD = 8
CS0_MEM_REG .short 0x2a0 ; 1 Dummy Cycle 16 bit 0 WS SW BP enable
CS1_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable
CS2_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable
CS3_MEM_REG .short 0x283 ; 1 Dummy Cycle 8 bit 3 WS SW BP enable
CS4_MEM_REG .short 0xe85 ; default reset value
.if CHIPSET = 3
.if OP_L1_STANDALONE = 1
CS6_MEM_REG .short 0x0c0 ; Internal RAM init : 0 WS, 32 bits, little, write enable
.endif
.elseif CHIPSET = 4
CS6_MEM_REG .short 0x0c0 ; Internal RAM init : 0 WS, 32 bits, little, write enable
CS7_MEM_REG .short 0x0c0 ; Internal RAM init : 0 WS, 32 bits, little, write enable
.elseif CHIPSET = 5
.if OP_L1_STANDALONE = 1
CS6_MEM_REG .short 0x0c0 ; Internal RAM init : 0 WS, 32 bits, little, write enable
.endif
.elseif CHIPSET = 6
.if OP_L1_STANDALONE = 1
CS6_MEM_REG .short 0x0c0 ; Internal RAM init : 0 WS, 32 bits, little, write enable
.endif
.elseif CHIPSET = 7 | CHIPSET = 8
CS6_MEM_REG .short 0x0c0 ; Internal RAM init : 0 WS, 32 bits, little, write enable
CS7_MEM_REG .short 0x040 ; Internal BOOT ROM init : 0 WS, 32 bits, little, write disable
.elseif CHIPSET = 10
.if OP_L1_STANDALONE = 1
CS6_MEM_REG .short 0x0c0 ; Internal RAM init : 0 WS, 32 bits, little, write enable
CS7_MEM_REG .short 0x040 ; Internal BOOT ROM init : 0 WS, 32 bits, little, write disable
.endif
.endif ; CHIPSET = 3, 4, 5, 6, 7, 8 or 10
.elseif BOARD = 9
CS0_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable
CS1_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable
CS2_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable
CS3_MEM_REG .short 0x283 ; 1 Dummy Cycle 8 bit 3 WS SW BP enable
CS4_MEM_REG .short 0xe85 ; default reset value
.if CHIPSET = 3
.if OP_L1_STANDALONE = 1
CS6_MEM_REG .short 0x0c0 ; Internal RAM init : 0 WS, 32 bits, little, write enable
.endif
.elseif CHIPSET = 4
CS6_MEM_REG .short 0x0c0 ; Internal RAM init : 0 WS, 32 bits, little, write enable
CS7_MEM_REG .short 0x0c0 ; Internal RAM init : 0 WS, 32 bits, little, write enable
.elseif CHIPSET = 5
.if OP_L1_STANDALONE = 1
CS6_MEM_REG .short 0x0c0 ; Internal RAM init : 0 WS, 32 bits, little, write enable
.endif
.elseif CHIPSET = 6
.if OP_L1_STANDALONE = 1
CS6_MEM_REG .short 0x0c0 ; Internal RAM init : 0 WS, 32 bits, little, write enable
.endif
.elseif CHIPSET = 7
CS6_MEM_REG .short 0x2c0 ; Internal RAM init : 0 WS, 32 bits, little, write enable
CS7_MEM_REG .short 0x040 ; Internal BOOT ROM init : 0 WS, 32 bits, little, write disable
.elseif CHIPSET = 8
CS6_MEM_REG .short 0x2c0 ; Internal RAM init : 0 WS, 32 bits, little, write enable
CS7_MEM_REG .short 0x040 ; Internal BOOT ROM init : 0 WS, 32 bits, little, write disable
.elseif CHIPSET = 10
.if OP_L1_STANDALONE = 1
CS6_MEM_REG .short 0x2c0 ; Internal RAM init : 0 WS, 32 bits, little, write enable
CS7_MEM_REG .short 0x040 ; Internal BOOT ROM init : 0 WS, 32 bits, little, write disable
.endif
.endif ; CHIPSET = 3, 4, 5, 6, 7, 8 or 10
.elseif BOARD = 35
CS0_MEM_REG .short 0x740 ; 7 WS, 32 bits, write disabled
CS1_MEM_REG .short 0x7C0 ; 7 WS, 32 bits, write enabled
CS2_MEM_REG .short 0x7C0 ; 7 WS, 32 bits, write enabled
CS6_MEM_REG .short 0x7C0 ; 7 WS, 32 bits, write enabled
CS7_MEM_REG .short 0x7C0 ; 7 WS, 32 bits, write enabled
API_ADAPT .equ 0x6A
CS7_SIZE .equ 0x2000 ; 8 kB
CS7_ADDR .equ 0x03800000 ; Initial address before toggling nIBOOT
SRAM_ADDR .equ 0x00800000 ; Internal SRAM start address
SRAM_SIZE .equ 0x00050000 ; 2.5 MBits
armio_in .word 0xFFFE4800 ; ARMIO_IN register address
armio_out .word 0xFFFE4802 ; ARMIO_OUT register address
addrExtraConf .word 0xFFFFFB10 ; Extra configuration
addrCS7 .word 0xFFFFFB08 ; CS7 configuration
DEF_EXTRA_CONF .short 0x033E ; Default configuration
EXTRA_CONF .short 0x013E ; Boot configuration
.elseif BOARD = 40
CS0_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 0 WS SW BP enable
CS1_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable
CS2_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable
CS3_MEM_REG .short 0x283 ; 1 Dummy Cycle 8 bit 3 WS SW BP enable
CS4_MEM_REG .short 0xe85 ; default reset value
.if CHIPSET = 8
CS6_MEM_REG .short 0x0c0 ; Internal RAM init : 0 WS, 32 bits, little, write enable
CS7_MEM_REG .short 0x040 ; Internal BOOT ROM init : 0 WS, 32 bits, little, write disable
.elseif CHIPSET = 10 | CHIPSET = 11
CS6_MEM_REG .short 0x0c0 ; Internal RAM init : 0 WS, 32 bits, little, write enable
CS7_MEM_REG .short 0x040 ; Internal BOOT ROM init : 0 WS, 32 bits, little, write disable
.endif ; CHIPSET = 8, 10 or 11
.elseif BOARD = 41
CS0_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable
CS1_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable
CS2_MEM_REG .short 0x2a1 ; 1 Dummy Cycle 16 bit 1 WS SW BP enable
CS3_MEM_REG .short 0x283 ; 1 Dummy Cycle 8 bit 3 WS SW BP enable
CS4_MEM_REG .short 0xe85 ; default reset value
.if CHIPSET = 8
CS6_MEM_REG .short 0x2c0 ; Internal RAM init : 0 WS, 32 bits, little, write enable
CS7_MEM_REG .short 0x040 ; Internal BOOT ROM init : 0 WS, 32 bits, little, write disable
.elseif CHIPSET = 10 | CHIPSET = 11
CS6_MEM_REG .short 0x2c0 ; Internal RAM init : 0 WS, 32 bits, little, write enable
CS7_MEM_REG .short 0x040 ; Internal BOOT ROM init : 0 WS, 32 bits, little, write disable
.endif ; CHIPSET = 8, 10 or 11
.elseif BOARD = 42
.if CHIPSET == 12
CS0_MEM_REG .short 0x2A1 ;RAM init : 1 WS, 16 bits, little
CS4_MEM_REG .short 0x2A1 ;RAM init : 1 WS, 16 bits, little
CS5_MEM_REG .short 0x2A1 ;ROM init : 0 WS, 16 bits, little
.endif ; CHIPSET = 12
.elseif BOARD = 43
.if CHIPSET = 12
CS0_MEM_REG .short 0x2A1 ;RAM init : 1 WS, 16 bits, little
CS5_MEM_REG .short 0x2A1 ;ROM init : 1 WS, 16 bits, little
CS4_MEM_REG .short 0x2A1 ;RAM init : 1 WS, 16 bits, little
.endif ; CHIPSET = 12
.elseif BOARD = 45
.if CHIPSET = 12
CS0_MEM_REG .short 0x2A1 ;RAM init : 1 WS, 16 bits, little
CS4_MEM_REG .short 0x2A1 ;RAM init : 1 WS, 16 bits, little
CS5_MEM_REG .short 0x2A1 ; init : 0 WS, 16 bits, little
.endif ; CHIPSET = 12
.elseif BOARD = 46
CS0_MEM_REG .short 0x7C0 ; 7 WS, 32 bits, write enabled
CS1_MEM_REG .short 0x7C0 ; 7 WS, 32 bits, write enabled
CS2_MEM_REG .short 0x7C0 ; 7 WS, 32 bits, write enabled
CS6_MEM_REG .short 0x7C0 ; 7 WS, 32 bits, write enabled
CS7_MEM_REG .short 0x7C0 ; 7 WS, 32 bits, write enabled
API_ADAPT .equ 0x6A
CS7_SIZE .equ 0x2000 ; 8 kB
CS7_ADDR .equ 0x03800000 ; Initial address before toggling nIBOOT
SRAM_ADDR .equ 0x00800000 ; Internal SRAM start address
SRAM_SIZE .equ 0x00050000 ; 2.5 MBits
armio_in .word 0xFFFE4800 ; ARMIO_IN register address
armio_out .word 0xFFFE4802 ; ARMIO_OUT register address
addrExtraConf .word 0xFFFFFB10 ; Extra configuration
addrCS7 .word 0xFFFFFB08 ; CS7 configuration
DEF_EXTRA_CONF .short 0x033E ; Default configuration
EXTRA_CONF .short 0x013E ; Boot configuration
.elseif BOARD = 70 | BOARD = 71
.if CHIPSET = 15
.if PSP_FAILSAFE = 1
CS0_MEM_REG .word 0x0000FFF9 ; Asynch Read/write, 15-RDWST,15-WRWST, 15-WELEN
CS3_MEM_REG .word 0x0000FFF9 ; Asynch Read/write, 4-RDWST,5-WRWST, 3-WELEN
.else
CS0_MEM_REG .word 0x00002031 ; Asynch Read/write, 3-RDWST,0-WRWST, 2-WELEN
CS3_MEM_REG .word 0x00002031 ; Asynch Read/write, 3-RDWST,0-WRWST, 2-WELEN
.endif
.endif
.endif ; BOARD 70
CLKM_MEM_REG .equ 0x31 ;the same define INIT_CLKM_ARM_CLK = 0x1031 for InitArmAfterReset
CTL_MEM_REG .short 0x02a ; rhea strobe 0/1 + API access size adaptation