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/************* Revision Controle System Header *************
* GSM Layer 1 software
* DYNAMIC_CLOCK_10_11_H
*
* Filename dynamic_clock_10_11.h
* Copyright 2003 (C) Texas Instruments
*
************* Revision Controle System Header *************/
/***********************************************************************************************
* Only SAMSON/CALYPSO families are considered for dynamic clock configuration.
***********************************************************************************************
*
* CHIPSET = 10 (CALYPSO C35)
* CHIPSET = 11 (CALYPSO LITE C035)
*
***********************************************************************************************
* Supported clock configuration
*
*
* CHIPSET 78/78/13 78/78/39 104/104/52 156/78/52 130/130/65
* (0) (1) (2) (3) (4)
*
* CALYPSO C035 (10) NA X X NA
* CALYPSO LITE C035 (11) NA X X NA
*
*
* BOARD CHIPSET Access Time (ns)
* CS0 CS1 CS2 CS3 CS4 CS5
*
* EVA4 (RAM) (6) CALYPSO C035 100 NA NA NA 100 NA
* D-Sample (RAM) (40) CALYPSO C035 85 70 70 NA (RD316, RD112) FLASH/SRAM : 28F640W30B70 (Intel) - SRAM : K1S321615M-EE10 (Samsung)
* D-Sample (FLASH) (41) CALYPSO C035 70 70 85 NA (RD316, RD112) FLASH/SRAM : 28F640W30B70 (Intel) - SRAM : K1S321615M-EE10 (Samsung)
*
***********************************************************************************************/
#include "chipset.cfg"
#include "board.cfg"
#if (CHIPSET == 10) || (CHIPSET == 11)
#ifndef _DYNAMIC_CLOCK_10_11_H_
#define _DYNAMIC_CLOCK_10_11_H_
#ifdef _DYNAMIC_CLOCK_C_
/***************************************************************************
* C_CLOCK_CFG_78_78_13 configuration
**************************************************************************/
/* Not applicable due to API 16-bits read problem */
/***************************************************************************
* C_CLOCK_CFG_78_78_39 configuration
**************************************************************************/
const T_DYNAMIC_CLOCK_CFG d_10_11_78_78_39_clock =
{
/* Index of the present clock configuration */
C_CLOCK_CFG_78_78_39,
/* DSP clock in kHz */
78000,
/* DPLL configuration */
DPLL_BYPASS_DIV_1, DPLL_LOCK_DIV_1, 6,
/* ARM clock configuration */
CLKM_SEL_DPLL, 2, CLKM_DISABLE_XP5,
/* DSP latencies configuration */
D_LAT_MCU_HOM2SAM,
D_LAT_MCU_BRIDGE,
D_LAT_MCU_BEF_FAST_ACCESS,
D_LAT_DSP_AFTER_SAM,
D_TRANSFER_RATE,
/* API-RHEA configuration */
/* API_WS */
0, 1,
/* RHEA Access Factor */
0, 0,
/* RHEA Timeout */
0xFF,
/* EMIF configuration */
#if (BOARD == 6)
{ 2, MEM_DVS_16, MEM_WRITE_EN, 0 }, // CS0
{ 2, MEM_DVS_8, MEM_WRITE_EN, 0 }, // CS1
{ 4, MEM_DVS_16, MEM_WRITE_EN, 0 }, // CS2
{ 5, MEM_DVS_8, MEM_WRITE_EN, 0 }, // CS3
{ 0, MEM_DVS_16, MEM_WRITE_EN, 0 }, // CS4
#elif (BOARD == 35) // P2-Sample / TEB OMAP730
{ 7, MEM_DVS_32, MEM_WRITE_EN, 0 }, // CS0
{ 7, MEM_DVS_32, MEM_WRITE_EN, 0 }, // CS1
{ 7, MEM_DVS_32, MEM_WRITE_EN, 0 }, // CS2
{ 7, MEM_DVS_32, MEM_WRITE_EN, 0 }, // CS3
{ 7, MEM_DVS_32, MEM_WRITE_EN, 0 }, // CS4
#elif (BOARD == 40) // D-Sample RAM
{ 4, MEM_DVS_16, MEM_WRITE_EN, 0 }, // CS0 - External SRAM
{ 3, MEM_DVS_16, MEM_WRITE_EN, 0 }, // CS1 - External SRAM 8Mbits
{ 3, MEM_DVS_16, MEM_WRITE_EN, 0 }, // CS2 - FLASH
{ 5, MEM_DVS_8, MEM_WRITE_EN, 0 }, // CS3
{ 0, MEM_DVS_8, MEM_WRITE_EN, 0 }, // CS4
#elif (BOARD == 41) // D-Sample FLASH
{ 3, MEM_DVS_16, MEM_WRITE_EN, 0 }, // CS0 - FLASH
{ 3, MEM_DVS_16, MEM_WRITE_EN, 0 }, // CS1 - External SRAM 8Mbits
{ 5, MEM_DVS_16, MEM_WRITE_EN, 0 }, // CS2 - External SRAM
{ 5, MEM_DVS_8, MEM_WRITE_EN, 0 }, // CS3
{ 0, MEM_DVS_8, MEM_WRITE_EN, 0 }, // CS4
#elif (BOARD == 46) // F-sample
{ 7, MEM_DVS_32, MEM_WRITE_EN, 0 }, // CS0
{ 7, MEM_DVS_32, MEM_WRITE_EN, 0 }, // CS1
{ 7, MEM_DVS_32, MEM_WRITE_EN, 0 }, // CS2
{ 7, MEM_DVS_32, MEM_WRITE_EN, 0 }, // CS3
{ 7, MEM_DVS_32, MEM_WRITE_EN, 0 }, // CS4
#else
#error "This BOARD configuration is not supported"
#endif
{ 0, MEM_DVS_32, MEM_WRITE_EN, 0 }, // CS6
{ 0, MEM_DVS_32, MEM_WRITE_DIS, 0 }, // CS7
};
/***************************************************************************
* C_CLOCK_CFG_104_104_52 configuration
**************************************************************************/
const T_DYNAMIC_CLOCK_CFG d_10_11_104_104_52_clock =
{
/* Index of the present clock configuration */
C_CLOCK_CFG_104_104_52,
/* DSP clock in kHz */
104000,
/* DPLL configuration */
DPLL_BYPASS_DIV_1, DPLL_LOCK_DIV_1, 8,
/* ARM clock configuration */
CLKM_SEL_DPLL, 2, CLKM_DISABLE_XP5,
/* DSP latencies configuration */
D_LAT_MCU_HOM2SAM,
D_LAT_MCU_BRIDGE,
D_LAT_MCU_BEF_FAST_ACCESS,
D_LAT_DSP_AFTER_SAM,
D_TRANSFER_RATE,
/* API-RHEA configuration */
/* API_WS */
0, 1,
/* RHEA Access Factor */
#if (BOARD ==35) //P2 sample needs two more wait state - see CQ16046
2, 2,
#else //BOARD
0, 0,
#endif //BOARD
/* RHEA Timeout */
0xFF,
/* EMIF configuration */
#if (BOARD == 6)
{ 3, MEM_DVS_16, MEM_WRITE_EN, 0 }, // CS0
{ 3, MEM_DVS_8, MEM_WRITE_EN, 0 }, // CS1
{ 6, MEM_DVS_16, MEM_WRITE_EN, 0 }, // CS2
{ 5, MEM_DVS_8, MEM_WRITE_EN, 0 }, // CS3
{ 0, MEM_DVS_16, MEM_WRITE_EN, 0 }, // CS4
#elif (BOARD == 35) // P2-Sample / TEB OMAP730
{ 7, MEM_DVS_32, MEM_WRITE_EN, 0 }, // CS0
{ 7, MEM_DVS_32, MEM_WRITE_EN, 0 }, // CS1
{ 7, MEM_DVS_32, MEM_WRITE_EN, 0 }, // CS2
{ 7, MEM_DVS_32, MEM_WRITE_EN, 0 }, // CS3
{ 7, MEM_DVS_32, MEM_WRITE_EN, 0 }, // CS4
#elif (BOARD == 40) // D-Sample RAM
{ 5, MEM_DVS_16, MEM_WRITE_EN, 0 }, // CS0 - External SRAM
{ 4, MEM_DVS_16, MEM_WRITE_EN, 0 }, // CS1 - External SRAM 8Mbits
{ 4, MEM_DVS_16, MEM_WRITE_EN, 0 }, // CS2 - FLASH
{ 5, MEM_DVS_8, MEM_WRITE_EN, 0 }, // CS3
{ 0, MEM_DVS_8, MEM_WRITE_EN, 0 }, // CS4
#elif (BOARD == 41) // D-Sample FLASH
{ 3, MEM_DVS_16, MEM_WRITE_EN, 0 }, // CS0 - FLASH
{ 3, MEM_DVS_16, MEM_WRITE_EN, 0 }, // CS1 - External SRAM 8Mbits
{ 5, MEM_DVS_16, MEM_WRITE_EN, 0 }, // CS2 - External SRAM
{ 5, MEM_DVS_8, MEM_WRITE_EN, 0 }, // CS3
{ 0, MEM_DVS_8, MEM_WRITE_EN, 0 }, // CS4
#elif (BOARD == 46) // F-sample
{ 7, MEM_DVS_32, MEM_WRITE_EN, 0 }, // CS0
{ 7, MEM_DVS_32, MEM_WRITE_EN, 0 }, // CS1
{ 7, MEM_DVS_32, MEM_WRITE_EN, 0 }, // CS2
{ 7, MEM_DVS_32, MEM_WRITE_EN, 0 }, // CS3
{ 7, MEM_DVS_32, MEM_WRITE_EN, 0 }, // CS4
#else
#error "This BOARD configuration is not supported"
#endif
{ 0, MEM_DVS_32, MEM_WRITE_EN, 0 }, // CS6
{ 0, MEM_DVS_32, MEM_WRITE_DIS, 0 }, // CS7
};
const T_DYNAMIC_CLOCK_CFG * a_dynamic_clock_cfg[C_NB_MAX_CLOCK_CONFIG] = {
&d_10_11_78_78_39_clock, /* 78/78/39 MHz */
&d_10_11_104_104_52_clock, /* 104/104/52 MHz */
(T_DYNAMIC_CLOCK_CFG *) NULL
};
#else
extern const T_DYNAMIC_CLOCK_CFG * a_dynamic_clock_cfg[C_NB_MAX_CLOCK_CONFIG];
#endif /* _DYNAMIC_CLOCK_C_ */
#endif /* _DYNAMIC_CLOCK_10_11_H_ */
#endif /* CHIPSET == 10 or 11 */