www.pudn.com > writemac.rar > dm643.c, change:2005-11-14,size:6831b
/* * Copyright 2003 by Spectrum Digital Incorporated. * All rights reserved. Property of Spectrum Digital Incorporated. */ /* * ======== dm643.c ======== * DM643 board initializion implementation. */ #include#include #include #include #include /*#include #include #include #include #include */ #include "dm643.h" /* I2C handle */ I2C_Handle DM643_I2C_hI2C; /* GPIO handle */ GPIO_Handle DM643_GPIO_hGPIO; /* Initialize the board APIs */ void DM643_init() { volatile Uint32 test; EMIFA_Config emifaCfg0 = { EMIFA_FMKS(GBLCTL, EK2RATE, HALFCLK) | EMIFA_FMKS(GBLCTL, EK2HZ, CLK) | EMIFA_FMKS(GBLCTL, EK2EN, ENABLE) | EMIFA_FMKS(GBLCTL, BRMODE, MRSTATUS) | EMIFA_FMKS(GBLCTL, NOHOLD, DISABLE) | EMIFA_FMKS(GBLCTL, EK1HZ, HIGHZ) | EMIFA_FMKS(GBLCTL, EK1EN, ENABLE) | EMIFA_FMKS(GBLCTL, CLK4EN, ENABLE) | EMIFA_FMKS(GBLCTL, CLK6EN, ENABLE), EMIFA_FMKS(CECTL, WRSETUP, DEFAULT) | EMIFA_FMKS(CECTL, WRSTRB, DEFAULT) | EMIFA_FMKS(CECTL, WRHLD, DEFAULT) | EMIFA_FMKS(CECTL, RDSETUP, DEFAULT) | EMIFA_FMKS(CECTL, TA, DEFAULT) | EMIFA_FMKS(CECTL, RDSTRB, DEFAULT) | EMIFA_FMKS(CECTL, MTYPE, SDRAM64) | EMIFA_FMKS(CECTL, RDHLD, DEFAULT), EMIFA_FMKS(CECTL, WRSETUP, OF(7)) | EMIFA_FMKS(CECTL, WRSTRB, OF(14)) | EMIFA_FMKS(CECTL, WRHLD, OF(2)) | EMIFA_FMKS(CECTL, RDSETUP, OF(2)) | EMIFA_FMKS(CECTL, TA, OF(2)) | EMIFA_FMKS(CECTL, RDSTRB, OF(14)) | EMIFA_FMKS(CECTL, MTYPE, ASYNC8) | EMIFA_FMKS(CECTL, RDHLD, OF(1)), EMIFA_FMKS(CECTL, WRSETUP, OF(2)) | EMIFA_FMKS(CECTL, WRSTRB, OF(10)) | EMIFA_FMKS(CECTL, WRHLD, OF(2)) | EMIFA_FMKS(CECTL, RDSETUP, OF(2)) | EMIFA_FMKS(CECTL, TA, OF(2)) | EMIFA_FMKS(CECTL, RDSTRB, OF(10)) | EMIFA_FMKS(CECTL, MTYPE, ASYNC8) | EMIFA_FMKS(CECTL, RDHLD, OF(2)), EMIFA_FMKS(CECTL, WRSETUP, OF(2)) | EMIFA_FMKS(CECTL, WRSTRB, OF(10)) | EMIFA_FMKS(CECTL, WRHLD, OF(2)) | EMIFA_FMKS(CECTL, RDSETUP, OF(2)) | EMIFA_FMKS(CECTL, TA, OF(2)) | EMIFA_FMKS(CECTL, RDSTRB, OF(10)) | EMIFA_FMKS(CECTL, MTYPE, ASYNC8) | EMIFA_FMKS(CECTL, RDHLD, OF(2)), EMIFA_FMKS(SDCTL, SDBSZ, 4BANKS) | EMIFA_FMKS(SDCTL, SDRSZ, 12ROW) | EMIFA_FMKS(SDCTL, SDCSZ, 8COL) | EMIFA_FMKS(SDCTL, RFEN, ENABLE) | EMIFA_FMKS(SDCTL, INIT, YES) | EMIFA_FMKS(SDCTL, TRCD, OF(1)) | EMIFA_FMKS(SDCTL, TRP, OF(1)) | EMIFA_FMKS(SDCTL, TRC, OF(5)) | EMIFA_FMKS(SDCTL, SLFRFR, DISABLE), EMIFA_FMKS(SDTIM, XRFR, OF(0)) | EMIFA_FMKS(SDTIM, PERIOD, OF(2075)), EMIFA_FMKS(SDEXT, WR2RD, OF(1)) | EMIFA_FMKS(SDEXT, WR2DEAC, OF(3)) | EMIFA_FMKS(SDEXT, WR2WR, OF(1)) | EMIFA_FMKS(SDEXT, R2WDQM, OF(3)) | EMIFA_FMKS(SDEXT, RD2WR, OF(2)) | EMIFA_FMKS(SDEXT, RD2DEAC, OF(3)) | EMIFA_FMKS(SDEXT, RD2RD, OF(1)) | EMIFA_FMKS(SDEXT, THZP, OF(2)) | EMIFA_FMKS(SDEXT, TWR, OF(2)) | EMIFA_FMKS(SDEXT, TRRD, OF(0)) | EMIFA_FMKS(SDEXT, TRAS, OF(6)) | EMIFA_FMKS(SDEXT, TCL, OF(1)), EMIFA_CESEC_DEFAULT, EMIFA_CESEC_DEFAULT, EMIFA_CESEC_DEFAULT, EMIFA_FMKS(CESEC, SNCCLK, ECLKOUT2) | EMIFA_FMKS(CESEC, RENEN, READ) | EMIFA_FMKS(CESEC, CEEXT, ACTIVE) | EMIFA_FMKS(CESEC, SYNCWL, 0CYCLE) | EMIFA_FMKS(CESEC, SYNCRL, 3CYCLE) }; I2C_Config i2cCfg = { 0x0000007f, /* I2COAR - Not used if master */ 0x00000000, /* I2CIER - Disable interrupts, use polling */ 0x0000001b, /* I2CCLKL - Low period for 100KHz operation */ 0x0000001b, /* I2CCLKH - High period for 100KHz operation */ 0x00000002, /* I2CCNT - Data words per transmission */ 0x0000001a, /* I2CSAR - Slave address */ 0x00004680, /* I2CMDR - Mode */ 0x00000019 /* I2CPSC - Prescale 300MHz to 12MHz */ }; /* Initialize CSL */ CSL_init(); /* Unlock PERCFG through PCFGLOCK */ *((unsigned long *)0x1b3f018) = 0x10c0010c; /* Enable VP0-VP2, I2C and McASP0 in PERCFG */ *((unsigned long *)0x1b3f000) = 0x69; /* Read back PERCFG */ test = *((unsigned long *)0x1b3f000); /* Wait at least 128 CPU cycles */ DM643_wait(128); /* Initialize EMIFA */ EMIFA_config(&emifaCfg0); /* Open I2C handle */ DM643_I2C_hI2C = I2C_open(I2C_PORT0, I2C_OPEN_RESET); /* Configure I2C controller */ I2C_config(DM643_I2C_hI2C, &i2cCfg); /* Take I2C out of reset */ I2C_outOfReset(DM643_I2C_hI2C); /* Open the GPIO handle */ DM643_GPIO_hGPIO = GPIO_open(GPIO_DEV0, GPIO_OPEN_RESET); /* Enable caching of SDRAM */ CACHE_enableCaching(CACHE_EMIFA_CE00); CACHE_enableCaching(CACHE_EMIFA_CE01); DM643_LED_init(); /* Load the FPGA from Flash */ //DM643_fpgaLoad(DM643_FPGAFLASH_BASE); /* Configure APLL in default state */ //DM643_APLL_rset(DM643_APLL_FSG0); } /* Read an 8-bit value from a CPLD register */ Uint8 DM643_rget(Int16 regnum) { Uint8 *pdata; // Return lower 8 bits of register pdata = (Uint8 *)(DM643_CPLD_BASE + regnum); //return (*pdata); return (*pdata & 0xff); } /* Write an 8-bit value to a CPLD register */ void DM643_rset(Int16 regnum, Uint8 regval) { Uint8 *pdata; // Write lower 8 bits of register pdata = (Uint8 *)(DM643_CPLD_BASE + regnum); *pdata = (regval & 0xff); } /* Spin in a delay loop for delay iterations */ void DM643_wait(Uint32 delay) { volatile Uint32 i, n; n = 0; for (i = 0; i < delay; i++) { n = n + 1; } } /* Spin in a delay loop for delay microseconds */ void DM643_waitusec(Uint32 delay) { DM643_wait(delay * 21); } void VDP_restart() { *(Uint32 *)MAPDOUT = 0x80; }