www.pudn.com > interupt.rar > interupt.flow.rpt


Flow report for interupt 
Thu Jun 19 11:36:18 2008 
Quartus II Version 7.2 Build 207 03/18/2008 Service Pack 3 SJ Full Version 
 
 
--------------------- 
; Table of Contents ; 
--------------------- 
  1. Legal Notice 
  2. Flow Summary 
  3. Flow Settings 
  4. Flow Non-Default Global Settings 
  5. Flow Elapsed Time 
  6. Flow Log 
 
 
 
---------------- 
; Legal Notice ; 
---------------- 
Copyright (C) 1991-2007 Altera Corporation 
Your use of Altera Corporation's design tools, logic functions  
and other software and tools, and its AMPP partner logic  
functions, and any output files from any of the foregoing  
(including device programming or simulation files), and any  
associated documentation or information are expressly subject  
to the terms and conditions of the Altera Program License  
Subscription Agreement, Altera MegaCore Function License  
Agreement, or other applicable license agreement, including,  
without limitation, that your use is for the sole purpose of  
programming logic devices manufactured by Altera and sold by  
Altera or its authorized distributors.  Please refer to the  
applicable agreement for further details. 
 
 
 
+--------------------------------------------------------------------------+ 
; Flow Summary                                                             ; 
+--------------------------+-----------------------------------------------+ 
; Flow Status              ; Successful - Thu Jun 19 11:36:18 2008         ; 
; Quartus II Version       ; 7.2 Build 207 03/18/2008 SP 3 SJ Full Version ; 
; Revision Name            ; interupt                                      ; 
; Top-level Entity Name    ; Block1                                        ; 
; Family                   ; Cyclone                                       ; 
; Device                   ; EP1C6Q240C8                                   ; 
; Timing Models            ; Final                                         ; 
; Met timing requirements  ; Yes                                           ; 
; Total logic elements     ; 3,114 / 5,980 ( 52 % )                        ; 
; Total pins               ; 53 / 185 ( 29 % )                             ; 
; Total virtual pins       ; 0                                             ; 
; Total memory bits        ; 46,848 / 92,160 ( 51 % )                      ; 
; DSP block 9-bit elements ; N/A until Partition Merge                     ; 
; Total PLLs               ; 1 / 2 ( 50 % )                                ; 
; Total DLLs               ; N/A until Partition Merge                     ; 
+--------------------------+-----------------------------------------------+ 
 
 
+-----------------------------------------+ 
; Flow Settings                           ; 
+-------------------+---------------------+ 
; Option            ; Setting             ; 
+-------------------+---------------------+ 
; Start date & time ; 06/19/2008 11:32:49 ; 
; Main task         ; Compilation         ; 
; Revision Name     ; interupt            ; 
+-------------------+---------------------+ 
 
 
+-----------------------------------------------------------------------------------------+ 
; Flow Non-Default Global Settings                                                        ; 
+------------------------------------+---------+---------------+-------------+------------+ 
; Assignment Name                    ; Value   ; Default Value ; Entity Name ; Section Id ; 
+------------------------------------+---------+---------------+-------------+------------+ 
; PARTITION_COLOR                    ; 2147039 ; --            ; Block1      ; Top        ; 
; PARTITION_NETLIST_TYPE             ; SOURCE  ; --            ; Block1      ; Top        ; 
; TOP_LEVEL_ENTITY                   ; Block1  ; interupt      ; --          ; --         ; 
; USE_GENERATED_PHYSICAL_CONSTRAINTS ; Off     ; --            ; --          ; eda_palace ; 
+------------------------------------+---------+---------------+-------------+------------+ 
 
 
+------------------------------------------------------------------+ 
; Flow Elapsed Time                                                ; 
+-------------------------+--------------+-------------------------+ 
; Module Name             ; Elapsed Time ; Average Processors Used ; 
+-------------------------+--------------+-------------------------+ 
; Analysis & Synthesis    ; 00:01:46     ; 1.0                     ; 
; Fitter                  ; 00:01:12     ; 1.0                     ; 
; Assembler               ; 00:00:04     ; 1.0                     ; 
; Classic Timing Analyzer ; 00:00:05     ; 1.0                     ; 
; Total                   ; 00:03:07     ; --                      ; 
+-------------------------+--------------+-------------------------+ 
 
 
------------ 
; Flow Log ; 
------------ 
quartus_map --read_settings_files=on --write_settings_files=off interupt -c interupt 
quartus_fit --read_settings_files=off --write_settings_files=off interupt -c interupt 
quartus_asm --read_settings_files=off --write_settings_files=off interupt -c interupt 
quartus_tan --read_settings_files=off --write_settings_files=off interupt -c interupt --timing_analysis_only