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--scfifo DEVICE_FAMILY="Cyclone" LPM_NUMWORDS=64 LPM_SHOWAHEAD="OFF" lpm_width=8 lpm_widthu=6 OPTIMIZE_FOR_SPEED=5 OVERFLOW_CHECKING="OFF" UNDERFLOW_CHECKING="OFF" USE_EAB="ON" aclr clock data empty full q rdreq usedw wrreq CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 CYCLONEII_M4K_COMPATIBILITY="ON" LOW_POWER_MODE="AUTO" lpm_hint="RAM_BLOCK_TYPE=AUTO" RAM_BLOCK_TYPE="AUTO" 
--VERSION_BEGIN 7.2SP3 cbx_altdpram 2007:04:25:14:55:30:SJ cbx_altsyncram 2007:08:27:07:35:30:SJ cbx_cycloneii 2007:06:13:15:47:32:SJ cbx_fifo_common 2007:04:09:14:30:26:SJ cbx_lpm_add_sub 2007:08:06:16:01:34:SJ cbx_lpm_compare 2007:06:21:15:54:06:SJ cbx_lpm_counter 2007:08:07:01:40:08:SJ cbx_lpm_decode 2007:03:12:19:01:52:SJ cbx_lpm_mux 2007:05:11:14:07:38:SJ cbx_mgl 2007:08:03:15:48:12:SJ cbx_scfifo 2007:04:06:15:45:12:SJ cbx_stratix 2007:10:18:20:36:46:SJ cbx_stratixii 2007:10:19:15:30:42:SJ cbx_stratixiii 2007:06:28:17:15:56:SJ cbx_util_mgl 2007:11:07:17:40:20:SJ  VERSION_END 
 
 
-- Copyright (C) 1991-2007 Altera Corporation 
--  Your use of Altera Corporation's design tools, logic functions  
--  and other software and tools, and its AMPP partner logic  
--  functions, and any output files from any of the foregoing  
--  (including device programming or simulation files), and any  
--  associated documentation or information are expressly subject  
--  to the terms and conditions of the Altera Program License  
--  Subscription Agreement, Altera MegaCore Function License  
--  Agreement, or other applicable license agreement, including,  
--  without limitation, that your use is for the sole purpose of  
--  programming logic devices manufactured by Altera and sold by  
--  Altera or its authorized distributors.  Please refer to the  
--  applicable agreement for further details. 
 
 
FUNCTION a_dpfifo_ml21 (aclr, clock, data[7..0], rreq, sclr, wreq) 
RETURNS ( empty, full, q[7..0], usedw[5..0]); 
 
--synthesis_resources = lut 20 M4K 1  
SUBDESIGN scfifo_ff21 
(  
	aclr	:	input; 
	clock	:	input; 
	data[7..0]	:	input; 
	empty	:	output; 
	full	:	output; 
	q[7..0]	:	output; 
	rdreq	:	input; 
	usedw[5..0]	:	output; 
	wrreq	:	input; 
)  
VARIABLE  
	dpfifo : a_dpfifo_ml21; 
	sclr	: NODE; 
 
BEGIN  
	dpfifo.aclr = aclr; 
	dpfifo.clock = clock; 
	dpfifo.data[] = data[]; 
	dpfifo.rreq = rdreq; 
	dpfifo.sclr = sclr; 
	dpfifo.wreq = wrreq; 
	empty = dpfifo.empty; 
	full = dpfifo.full; 
	q[] = dpfifo.q[]; 
	sclr = GND; 
	usedw[] = dpfifo.usedw[]; 
END; 
--VALID FILE