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--altmult_add ADDNSUB_MULTIPLIER_PIPELINE_ACLR1="ACLR3" ADDNSUB_MULTIPLIER_PIPELINE_REGISTER1="CLOCK0" ADDNSUB_MULTIPLIER_REGISTER1="UNREGISTERED" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEDICATED_MULTIPLIER_CIRCUITRY="NO" DEVICE_FAMILY="Cyclone" DSP_BLOCK_BALANCING="Auto" INPUT_REGISTER_A0="UNREGISTERED" INPUT_REGISTER_B0="UNREGISTERED" INPUT_SOURCE_A0="DATAA" INPUT_SOURCE_B0="DATAB" MULTIPLIER1_DIRECTION="ADD" MULTIPLIER_ACLR0="ACLR3" MULTIPLIER_REGISTER0="CLOCK0" NUMBER_OF_MULTIPLIERS=1 OUTPUT_REGISTER="UNREGISTERED" port_addnsub1="PORT_UNUSED" port_signa="PORT_UNUSED" port_signb="PORT_UNUSED" REPRESENTATION_A="UNSIGNED" REPRESENTATION_B="UNSIGNED" SIGNED_PIPELINE_ACLR_A="ACLR3" SIGNED_PIPELINE_ACLR_B="ACLR3" SIGNED_PIPELINE_REGISTER_A="CLOCK0" SIGNED_PIPELINE_REGISTER_B="CLOCK0" SIGNED_REGISTER_A="UNREGISTERED" SIGNED_REGISTER_B="UNREGISTERED" WIDTH_A=32 WIDTH_B=4 WIDTH_RESULT=32 aclr3 clock0 dataa datab result CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 
--VERSION_BEGIN 7.2SP3 cbx_alt_ded_mult_y 2007:03:05:16:04:08:SJ cbx_altmult_add 2007:08:27:13:54:20:SJ cbx_cycloneii 2007:06:13:15:47:32:SJ cbx_lpm_add_sub 2007:08:06:16:01:34:SJ cbx_lpm_mult 2007:07:20:16:47:26:SJ cbx_mgl 2007:08:03:15:48:12:SJ cbx_padd 2007:07:12:14:48:24:SJ cbx_parallel_add 2007:01:30:03:53:08:SJ cbx_stratix 2007:10:18:20:36:46:SJ cbx_stratixii 2007:10:19:15:30:42:SJ cbx_util_mgl 2007:11:07:17:40:20:SJ  VERSION_END 
 
 
-- Copyright (C) 1991-2007 Altera Corporation 
--  Your use of Altera Corporation's design tools, logic functions  
--  and other software and tools, and its AMPP partner logic  
--  functions, and any output files from any of the foregoing  
--  (including device programming or simulation files), and any  
--  associated documentation or information are expressly subject  
--  to the terms and conditions of the Altera Program License  
--  Subscription Agreement, Altera MegaCore Function License  
--  Agreement, or other applicable license agreement, including,  
--  without limitation, that your use is for the sole purpose of  
--  programming logic devices manufactured by Altera and sold by  
--  Altera or its authorized distributors.  Please refer to the  
--  applicable agreement for further details. 
 
 
FUNCTION mac_mult_kmm (aclr[3..0], clk[3..0], dataa[31..0], datab[3..0], ena[3..0], signa, signb) 
RETURNS ( dataout[35..0]); 
FUNCTION mac_out_hsd (aclr[3..0], clk[3..0], dataa[35..0], ena[3..0], signa, signb) 
RETURNS ( dataout[35..0]); 
 
--synthesis_resources = lut 221  
SUBDESIGN mult_add_ovq2 
(  
	aclr3	:	input; 
	clock0	:	input; 
	dataa[31..0]	:	input; 
	datab[3..0]	:	input; 
	result[31..0]	:	output; 
)  
VARIABLE  
	mac_mult1 : mac_mult_kmm; 
	mac_out2 : mac_out_hsd; 
	aclr0	: NODE; 
	aclr1	: NODE; 
	aclr2	: NODE; 
	clock1	: NODE; 
	clock2	: NODE; 
	clock3	: NODE; 
	dataa_bus[31..0]	: WIRE; 
	datab_bus[3..0]	: WIRE; 
	ena0	: NODE; 
	ena1	: NODE; 
	ena2	: NODE; 
	ena3	: NODE; 
 
BEGIN  
	mac_mult1.aclr[] = ( aclr3, aclr2, aclr1, aclr0); 
	mac_mult1.clk[] = ( clock3, clock2, clock1, clock0); 
	mac_mult1.dataa[] = ( dataa_bus[31..0]); 
	mac_mult1.datab[] = ( datab_bus[3..0]); 
	mac_mult1.ena[] = ( ena3, ena2, ena1, ena0); 
	mac_mult1.signa = B"0"; 
	mac_mult1.signb = B"0"; 
	mac_out2.aclr[] = ( aclr3, aclr2, aclr1, aclr0); 
	mac_out2.clk[] = ( clock3, clock2, clock1, clock0); 
	mac_out2.dataa[] = ( mac_mult1.dataout[35..0]); 
	mac_out2.ena[] = ( ena3, ena2, ena1, ena0); 
	mac_out2.signa = B"0"; 
	mac_out2.signb = B"0"; 
	aclr0 = GND; 
	aclr1 = GND; 
	aclr2 = GND; 
	clock1 = VCC; 
	clock2 = VCC; 
	clock3 = VCC; 
	dataa_bus[] = ( dataa[31..0]); 
	datab_bus[] = ( datab[3..0]); 
	ena0 = VCC; 
	ena1 = VCC; 
	ena2 = VCC; 
	ena3 = VCC; 
	result[31..0] = mac_out2.dataout[31..0]; 
END; 
--VALID FILE