www.pudn.com > interupt.rar > mac_mult_kmm.tdf
--alt_mac_mult CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DATAA_WIDTH=32 DATAB_WIDTH=4 MULT_REPRESENTATION_A="UNSIGNED" MULT_REPRESENTATION_B="UNSIGNED" OUTPUT_CLEAR="A_3" OUTPUT_CLOCK="A_0" OUTPUT_WIDTH=36 aclr clk dataa datab dataout ena signa signb --VERSION_BEGIN 7.2SP3 cbx_alt_mac_mult 2006:11:15:14:22:14:SJ cbx_mgl 2007:08:03:15:48:12:SJ VERSION_END -- Copyright (C) 1991-2007 Altera Corporation -- Your use of Altera Corporation's design tools, logic functions -- and other software and tools, and its AMPP partner logic -- functions, and any output files from any of the foregoing -- (including device programming or simulation files), and any -- associated documentation or information are expressly subject -- to the terms and conditions of the Altera Program License -- Subscription Agreement, Altera MegaCore Function License -- Agreement, or other applicable license agreement, including, -- without limitation, that your use is for the sole purpose of -- programming logic devices manufactured by Altera and sold by -- Altera or its authorized distributors. Please refer to the -- applicable agreement for further details. FUNCTION mult_4hm (dataa[31..0], datab[3..0]) RETURNS ( result[35..0]); --synthesis_resources = lut 221 SUBDESIGN mac_mult_kmm ( aclr[3..0] : input; clk[3..0] : input; dataa[31..0] : input; datab[3..0] : input; dataout[35..0] : output; ena[3..0] : input; signa : input; signb : input; ) VARIABLE output_reg[35..0] : dffe; mult3 : mult_4hm; tmp_dataout[35..0] : WIRE; x_dataa[31..0] : WIRE; x_datab[3..0] : WIRE; x_output[35..0] : WIRE; BEGIN output_reg[].clk = clk[0..0]; output_reg[].clrn = (! aclr[3..3]); output_reg[].d = mult3.result[35..0]; output_reg[].ena = ena[0..0]; mult3.dataa[] = x_dataa[]; mult3.datab[] = x_datab[]; dataout[] = tmp_dataout[]; tmp_dataout[] = (x_output[] & (((signa # (! signa)) # signb) # (! signb))); x_dataa[] = ( dataa[]); x_datab[] = ( datab[]); x_output[] = output_reg[].q; END; --VALID FILE