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|uart_top finish_F <= uart_emitter:uart_emitter_a.port1 bit_counter[0] <= uart_receive:uart_receiver_a.port1 bit_counter[1] <= uart_receive:uart_receiver_a.port1 bit_counter[2] <= uart_receive:uart_receiver_a.port1 bit_counter[3] <= uart_receive:uart_receiver_a.port1 counter[0] <= uart_receive:uart_receiver_a.port3 counter[1] <= uart_receive:uart_receiver_a.port3 counter[2] <= uart_receive:uart_receiver_a.port3 counter[3] <= uart_receive:uart_receiver_a.port3 bus[0] <= uart_receive:uart_receiver_a.port0 bus[1] <= uart_receive:uart_receiver_a.port0 bus[2] <= uart_receive:uart_receiver_a.port0 bus[3] <= uart_receive:uart_receiver_a.port0 bus[4] <= uart_receive:uart_receiver_a.port0 bus[5] <= uart_receive:uart_receiver_a.port0 bus[6] <= uart_receive:uart_receiver_a.port0 bus[7] <= uart_receive:uart_receiver_a.port0 error <= uart_receive:uart_receiver_a.port2 finish_s <= uart_receive:uart_receiver_a.port4 serial <= serial~0.DB_MAX_OUTPUT_PORT_TYPE clock <= clock~0.DB_MAX_OUTPUT_PORT_TYPE sample_clock <= sample_clock~0.DB_MAX_OUTPUT_PORT_TYPE sys_clock => sys_clock~0.IN1 rest => rest~0.IN3 sel_baud_rate[0] => sel_baud_rate[0]~2.IN1 sel_baud_rate[1] => sel_baud_rate[1]~1.IN1 sel_baud_rate[2] => sel_baud_rate[2]~0.IN1 load_bus_reg => load_bus_reg~0.IN1 date_bus[0] => date_bus[0]~7.IN1 date_bus[1] => date_bus[1]~6.IN1 date_bus[2] => date_bus[2]~5.IN1 date_bus[3] => date_bus[3]~4.IN1 date_bus[4] => date_bus[4]~3.IN1 date_bus[5] => date_bus[5]~2.IN1 date_bus[6] => date_bus[6]~1.IN1 date_bus[7] => date_bus[7]~0.IN1 |uart_top|uart_clk:uart_clk_gen_a sel_baud_rate[0] => sel_baud_rate[0]~2.IN1 sel_baud_rate[1] => sel_baud_rate[1]~1.IN1 sel_baud_rate[2] => sel_baud_rate[2]~0.IN1 sys_clock => sys_clock~0.IN1 rest => rest~0.IN2 clock <= divide_by_256:divide_256.port0 sample_clock <= divide_by_256:divide_256.port1 |uart_top|uart_clk:uart_clk_gen_a|divide_by_13:divide_13 sys_clock_by_13 <= temp[3].DB_MAX_OUTPUT_PORT_TYPE sys_clock => temp[2].CLK sys_clock => temp[1].CLK sys_clock => temp[0].CLK sys_clock => temp[3].CLK rest => temp[2].ACLR rest => temp[1].ACLR rest => temp[0].ACLR rest => temp[3].ACLR |uart_top|uart_clk:uart_clk_gen_a|divide_by_256:divide_256 clock <= Select~0.DB_MAX_OUTPUT_PORT_TYPE sample_clk <= temp0[2].DB_MAX_OUTPUT_PORT_TYPE sel_baud_rate[0] => Decoder~0.IN2 sel_baud_rate[1] => Decoder~0.IN1 sel_baud_rate[2] => Decoder~0.IN0 sys_clock_13 => temp[6].CLK sys_clock_13 => temp[5].CLK sys_clock_13 => temp[4].CLK sys_clock_13 => temp[3].CLK sys_clock_13 => temp[2].CLK sys_clock_13 => temp[1].CLK sys_clock_13 => temp[0].CLK sys_clock_13 => temp[7].CLK rest => temp[6].ACLR rest => temp[5].ACLR rest => temp[4].ACLR rest => temp[3].ACLR rest => temp[2].ACLR rest => temp[1].ACLR rest => temp[0].ACLR rest => temp0[3].ACLR rest => temp0[2].ACLR rest => temp0[1].ACLR rest => temp0[0].ACLR rest => temp[7].ACLR |uart_top|uart_emitter:uart_emitter_a serial <= serial~reg0.DB_MAX_OUTPUT_PORT_TYPE finish_F <= finish_F~reg0.DB_MAX_OUTPUT_PORT_TYPE bus[0] => bus_reg[0].DATAIN bus[1] => bus_reg[1].DATAIN bus[2] => bus_reg[2].DATAIN bus[3] => bus_reg[3].DATAIN bus[4] => bus_reg[4].DATAIN bus[5] => bus_reg[5].DATAIN bus[6] => bus_reg[6].DATAIN bus[7] => bus_reg[7].DATAIN clock => serial~reg0.CLK clock => finish_F~reg0.CLK clock => bus_reg[7].CLK clock => bus_reg[6].CLK clock => bus_reg[5].CLK clock => bus_reg[4].CLK clock => bus_reg[3].CLK clock => bus_reg[2].CLK clock => bus_reg[1].CLK clock => bus_reg[0].CLK clock => state~1.IN1 rest => serial~reg0.PRESET rest => finish_F~reg0.ACLR rest => state~2.IN1 load_bus_reg => state~0.DATAB load_bus_reg => Select~0.IN2 |uart_top|uart_receive:uart_receiver_a bus[0] <= bus[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE bus[1] <= bus[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE bus[2] <= bus[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE bus[3] <= bus[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE bus[4] <= bus[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE bus[5] <= bus[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE bus[6] <= bus[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE bus[7] <= bus[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE bit_counter[0] <= bit_counter[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE bit_counter[1] <= bit_counter[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE bit_counter[2] <= bit_counter[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE bit_counter[3] <= bit_counter[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE error <= error~reg0.DB_MAX_OUTPUT_PORT_TYPE counter[0] <= counter[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE counter[1] <= counter[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE counter[2] <= counter[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE counter[3] <= counter[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE finish_s <= finish_s~reg0.DB_MAX_OUTPUT_PORT_TYPE serial => counter~4.OUTPUTSELECT serial => counter~5.OUTPUTSELECT serial => counter~6.OUTPUTSELECT serial => counter~7.OUTPUTSELECT serial => state~1.OUTPUTSELECT serial => bus_reg[7].DATAIN clk => finish_s~reg0.CLK clk => bit_counter[3]~reg0.CLK clk => bit_counter[2]~reg0.CLK clk => bit_counter[1]~reg0.CLK clk => bit_counter[0]~reg0.CLK clk => counter[3]~reg0.CLK clk => counter[2]~reg0.CLK clk => counter[1]~reg0.CLK clk => counter[0]~reg0.CLK clk => bus[7]~reg0.CLK clk => bus[6]~reg0.CLK clk => bus[5]~reg0.CLK clk => bus[4]~reg0.CLK clk => bus[3]~reg0.CLK clk => bus[2]~reg0.CLK clk => bus[1]~reg0.CLK clk => bus[0]~reg0.CLK clk => error~reg0.CLK clk => bus_reg[7].CLK clk => bus_reg[6].CLK clk => bus_reg[5].CLK clk => bus_reg[4].CLK clk => bus_reg[3].CLK clk => bus_reg[2].CLK clk => bus_reg[1].CLK clk => bus_reg[0].CLK clk => state.CLK rest => finish_s~reg0.ACLR rest => bit_counter[3]~reg0.ACLR rest => bit_counter[2]~reg0.ACLR rest => bit_counter[1]~reg0.ACLR rest => bit_counter[0]~reg0.ACLR rest => counter[3]~reg0.ACLR rest => counter[2]~reg0.ACLR rest => counter[1]~reg0.ACLR rest => counter[0]~reg0.ACLR rest => state.ACLR