www.pudn.com > uart.rar > uart_clk.hier_info

|uart_clk 
sel_baud_rate[0] => sel_baud_rate[0]~2.IN1 
sel_baud_rate[1] => sel_baud_rate[1]~1.IN1 
sel_baud_rate[2] => sel_baud_rate[2]~0.IN1 
sys_clock => sys_clock~0.IN1 
rest => rest~0.IN2 
clock <= divide_by_256:divide_256.port0 
sample_clock <= divide_by_256:divide_256.port1 
 
 
|uart_clk|divide_by_13:divide_13 
sys_clock_by_13 <= temp[3].DB_MAX_OUTPUT_PORT_TYPE 
sys_clock => temp[2].CLK 
sys_clock => temp[1].CLK 
sys_clock => temp[0].CLK 
sys_clock => temp[3].CLK 
rest => temp[2].ACLR 
rest => temp[1].ACLR 
rest => temp[0].ACLR 
rest => temp[3].ACLR 
 
 
|uart_clk|divide_by_256:divide_256 
clock <= Select~0.DB_MAX_OUTPUT_PORT_TYPE 
sample_clk <= temp0[2].DB_MAX_OUTPUT_PORT_TYPE 
sel_baud_rate[0] => Decoder~0.IN2 
sel_baud_rate[1] => Decoder~0.IN1 
sel_baud_rate[2] => Decoder~0.IN0 
sys_clock_13 => temp[6].CLK 
sys_clock_13 => temp[5].CLK 
sys_clock_13 => temp[4].CLK 
sys_clock_13 => temp[3].CLK 
sys_clock_13 => temp[2].CLK 
sys_clock_13 => temp[1].CLK 
sys_clock_13 => temp[0].CLK 
sys_clock_13 => temp[7].CLK 
rest => temp[6].ACLR 
rest => temp[5].ACLR 
rest => temp[4].ACLR 
rest => temp[3].ACLR 
rest => temp[2].ACLR 
rest => temp[1].ACLR 
rest => temp[0].ACLR 
rest => temp0[3].ACLR 
rest => temp0[2].ACLR 
rest => temp0[1].ACLR 
rest => temp0[0].ACLR 
rest => temp[7].ACLR