www.pudn.com > usbboot-v1.2.rar.zip > board.c, change:2008-03-01,size:5162b
/*
* board.c
*
* Board init routines.
*
* Copyright (C) 2006 Ingenic Semiconductor Inc.
*
*/
#include "jz4740.h"
#include "configs.h"
//These define in configs.h
//just modify configs.h
#if 0
#define CFG_CPU_SPEED 336000000 /* CPU clock: 384 MHz */
#define CFG_EXTAL 12000000 /* EXTAL freq: 12 MHz */
// SDRAM paramters
#define SDRAM_BW16 0 /* Data bus width: 0-32bit, 1-16bit */
#define SDRAM_BANK4 1 /* Banks each chip: 0-2bank, 1-4bank */
#define SDRAM_ROW 13 /* Row address: 11 to 13 */
#define SDRAM_COL 9 /* Column address: 8 to 12 */
#define SDRAM_CASL 2 /* CAS latency: 2 or 3 */
#endif
void leds(char *s)
{
volatile unsigned char* led = (unsigned char *)0xb6000058;
int i = 0;
while ( s[i] && (i < 8)) {
led[i] = s[i];
i++;
}
while (i < 8)
led[i++] = ' ';
}
void gpio_init(void)
{
/*
* Initialize SDRAM pins
*/
/* PORT A: D0 ~ D31 */
REG_GPIO_PXFUNS(0) = 0xffffffff;
REG_GPIO_PXSELC(0) = 0xffffffff;
/* PORT B: A0 ~ A16, DCS#, RAS#, CAS#, CKE#, RDWE#, CKO#, WE0# */
REG_GPIO_PXFUNS(1) = 0x81f9ffff;
REG_GPIO_PXSELC(1) = 0x81f9ffff;
/* PORT C: WE1#, WE2#, WE3# */
REG_GPIO_PXFUNS(2) = 0x07000000;
REG_GPIO_PXSELC(2) = 0x07000000;
/*
* Initialize Static Memory Pins
*/
/* CS4# */
REG_GPIO_PXFUNS(1) = 0x10000000;
REG_GPIO_PXSELC(1) = 0x10000000;
/*
* Initialize UART0 pins
*/
/* PORT D: TXD/RXD */
REG_GPIO_PXFUNS(3) = 0x06000000;
REG_GPIO_PXSELS(3) = 0x06000000;
/*
* Initialize LED pins
*/
/* PORT B: CS2# */
REG_GPIO_PXFUNS(1) = 0x04000000;
REG_GPIO_PXSELC(1) = 0x04000000;
}
void pll_init(void)
{
register unsigned int cfcr, plcr1;
int n2FR[33] = {
0, 0, 1, 2, 3, 0, 4, 0, 5, 0, 0, 0, 6, 0, 0, 0,
7, 0, 0, 0, 0, 0, 0, 0, 8, 0, 0, 0, 0, 0, 0, 0,
9
};
//int div[5] = {1, 4, 4, 4, 4}; /* divisors of I:S:P:L:M */
int div[5] = {1, 3, 3, 3, 3}; /* divisors of I:S:P:L:M */
int nf, pllout2;
cfcr = CPM_CPCCR_CLKOEN |
(n2FR[div[0]] << CPM_CPCCR_CDIV_BIT) |
(n2FR[div[1]] << CPM_CPCCR_HDIV_BIT) |
(n2FR[div[2]] << CPM_CPCCR_PDIV_BIT) |
(n2FR[div[3]] << CPM_CPCCR_MDIV_BIT) |
(n2FR[div[4]] << CPM_CPCCR_LDIV_BIT);
pllout2 = (cfcr & CPM_CPCCR_PCS) ? CFG_CPU_SPEED : (CFG_CPU_SPEED / 2);
/* Init UHC clock */
//REG_CPM_UHCCDR = pllout2 / 48000000 - 1;
nf = CFG_CPU_SPEED * 2 / CFG_EXTAL;
plcr1 = ((nf - 2) << CPM_CPPCR_PLLM_BIT) | /* FD */
(0 << CPM_CPPCR_PLLN_BIT) | /* RD=0, NR=2 */
(0 << CPM_CPPCR_PLLOD_BIT) | /* OD=0, NO=1 */
(0x20 << CPM_CPPCR_PLLST_BIT) | /* PLL stable time */
CPM_CPPCR_PLLEN; /* enable PLL */
/* init PLL */
REG_CPM_CPCCR = cfcr;
REG_CPM_CPPCR = plcr1;
}
//----------------------------------------------------------------------------
// SDRAM Timings, unit: ns
#define SDRAM_TRAS 45 /* RAS# Active Time */
#define SDRAM_RCD 20 /* RAS# to CAS# Delay */
#define SDRAM_TPC 20 /* RAS# Precharge Time */
#define SDRAM_TRWL 7 /* Write Latency Time */
#define SDRAM_TREF 15625 /* Refresh period: 4096 refresh cycles/64ms */
#define CPU_CLK 8000000
#define MEM_CLK 8000000
void sdram_init(void)
{
register unsigned int dmcr, sdmode, tmp, cpu_clk, mem_clk, ns;
volatile unsigned int delay;
unsigned int cas_latency_sdmr[2] = {
EMC_SDMR_CAS_2,
EMC_SDMR_CAS_3,
};
unsigned int cas_latency_dmcr[2] = {
1 << EMC_DMCR_TCL_BIT, /* CAS latency is 2 */
2 << EMC_DMCR_TCL_BIT /* CAS latency is 3 */
};
int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
cpu_clk = CFG_CPU_SPEED;
mem_clk = cpu_clk * div[__cpm_get_cdiv()] / div[__cpm_get_mdiv()];
REG_EMC_RTCSR = EMC_RTCSR_CKS_DISABLE;
REG_EMC_RTCOR = 0;
REG_EMC_RTCNT = 0;
/* Basic DMCR register value. */
dmcr = ((SDRAM_ROW-11)<<EMC_DMCR_RA_BIT) |
((SDRAM_COL-8)<<EMC_DMCR_CA_BIT) |
(SDRAM_BANK4<<EMC_DMCR_BA_BIT) |
(SDRAM_BW16<<EMC_DMCR_BW_BIT) |
EMC_DMCR_EPIN |
cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)];
/* SDRAM timimg parameters */
ns = 1000000000 / mem_clk;
tmp = SDRAM_TRAS/ns;
if (tmp < 4) tmp = 4;
if (tmp > 11) tmp = 11;
dmcr |= ((tmp-4) << EMC_DMCR_TRAS_BIT);
tmp = SDRAM_RCD/ns;
if (tmp > 3) tmp = 3;
dmcr |= (tmp << EMC_DMCR_RCD_BIT);
tmp = SDRAM_TPC/ns;
if (tmp > 7) tmp = 7;
dmcr |= (tmp << EMC_DMCR_TPC_BIT);
tmp = SDRAM_TRWL/ns;
if (tmp > 3) tmp = 3;
dmcr |= (tmp << EMC_DMCR_TRWL_BIT);
tmp = (SDRAM_TRAS + SDRAM_TPC)/ns;
if (tmp > 14) tmp = 14;
dmcr |= (((tmp + 1) >> 1) << EMC_DMCR_TRC_BIT);
/* First, precharge phase */
REG_EMC_DMCR = dmcr;
/* Set refresh registers */
tmp = SDRAM_TREF/ns;
tmp = tmp/64 + 1;
if (tmp > 0xff) tmp = 0xff;
REG_EMC_RTCOR = tmp;
REG_EMC_RTCSR = EMC_RTCSR_CKS_64; /* Divisor is 64, CKO/64 */
/* SDRAM mode values */
sdmode = EMC_SDMR_BT_SEQ |
EMC_SDMR_OM_NORMAL |
EMC_SDMR_BL_4 |
cas_latency_sdmr[((SDRAM_CASL == 3) ? 1 : 0)];
/* precharge all chip-selects */
REG8(EMC_SDMR0|sdmode) = 0;
/* wait for precharge, > 200us */
delay = (cpu_clk / 1000000) * 200;
while (delay--);
/* enable refresh and set SDRAM mode */
REG_EMC_DMCR = dmcr | EMC_DMCR_RFSH | EMC_DMCR_MRSET;
/* write sdram mode register for each chip-select */
REG8(EMC_SDMR0|sdmode) = 0;
/* everything is ok now */
}