www.pudn.com > encode.rar > encode.v

module encode(sample_clk,
             syn_global_reset,
             send,
             stop_encode,
             q_from_crc,
             q_from_shiftreg,
             ena_crc_send,
             ena_regs_send,
             qout_encode,
             data_shift_encode);
//recent modification:4/14
//output ports modified to internal ports:state,nextstate
input sample_clk;
input syn_global_reset;
input send;
input stop_encode;

input q_from_crc;
input q_from_shiftreg;
input ena_crc_send;
input ena_regs_send;

output qout_encode;
reg qout_encode;

reg [3:1] state;
reg [3:1] nextstate;

output data_shift_encode;


parameter S1=3'b000,
          S2=3'b001,
          S3=3'b010,
          S4=3'b011,
          Wait=3'b100;

assign data_shift_encode=(state==S1)||(state==S4);


wire qin_encode;
assign qin_encode=(ena_regs_send)?q_from_shiftreg:
                             (ena_crc_send)?(~q_from_crc):1'b?;

always @(posedge sample_clk)
begin 
  if(syn_global_reset)
    begin 
      state<=Wait;
    end
  else 
    begin 
     state<=nextstate;
    end
end

always@(state or qin_encode or send or stop_encode )
begin
   case(state)
      S1:begin
            if(qin_encode==1'b0)
               begin
                  nextstate<=S2;
               end
             else 
                begin
                   nextstate<=S3;
                end
         end
      S2:begin
            if(stop_encode)
               begin
                   nextstate<=Wait;
               end
            else
               begin
                  nextstate<=S1;
               end
         end
      S3:begin
             if(stop_encode)
                begin
                    nextstate<=Wait;
                end
             else
                begin
                  nextstate<=S4;
                end
         end
      S4:begin
            if(qin_encode==1'b0)
               begin
                  nextstate<=S3;
               end
            else 
               begin
                  nextstate<=S2;
               end
         end
      Wait:begin
              if(send)
                 begin
                     nextstate<=S1;
                 end
              else
                 begin
                     nextstate<=Wait;
                 end
           end
      default:begin
                 nextstate<=Wait;
              end
    endcase
end

always@(state)
begin
   case(state)
      S1:begin
            qout_encode<=1'b0;
         end
      S2:begin
            qout_encode<=1'b1;
         end
      S3:begin
            qout_encode<=1'b0;
         end
      S4:begin
            qout_encode<=1'b1;
         end
      Wait:begin
            qout_encode<=1'b0;
         end
      default:begin
                 qout_encode<=1'b0;
              end
    endcase
end

endmodule