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# Copyright (C) 1991-2005 Altera Corporation 
# Your use of Altera Corporation's design tools, logic functions  
# and other software and tools, and its AMPP partner logic        
# functions, and any output files any of the foregoing            
# (including device programming or simulation files), and any     
# associated documentation or information are expressly subject   
# to the terms and conditions of the Altera Program License       
# Subscription Agreement, Altera MegaCore Function License        
# Agreement, or other applicable license agreement, including,    
# without limitation, that your use is for the sole purpose of    
# programming logic devices manufactured by Altera and sold by    
# Altera or its authorized distributors.  Please refer to the     
# applicable agreement for further details. 
 
 
# The default values for assignments are stored in the file 
#		dds_assignment_defaults.qdf 
# If this file doesn't exist, and for assignments not listed, see file 
#		assignment_defaults.qdf 
 
# Altera recommends that you do not modify this file. This 
# file is updated automatically by the Quartus II software 
# and any changes you make may be lost or overwritten. 
 
 
# Project-Wide Assignments 
# ======================== 
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "5.0 SP1" 
set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:25:02  JUNE 17, 2008" 
set_global_assignment -name LAST_QUARTUS_VERSION 6.0 
set_global_assignment -name VHDL_FILE SUM99.vhd 
set_global_assignment -name VHDL_FILE DDS.vhd 
set_global_assignment -name VHDL_FILE REG1.vhd 
set_global_assignment -name VHDL_FILE REG2.vhd 
set_global_assignment -name VHDL_FILE ROM.vhd 
 
# Analysis & Synthesis Assignments 
# ================================ 
set_global_assignment -name FAMILY ACEX1K 
set_global_assignment -name TOP_LEVEL_ENTITY dds 
 
# Fitter Assignments 
# ================== 
set_global_assignment -name DEVICE "EP1K100QC208-3"