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--REG1.VHD 
LIBRARY IEEE; 
USE IEEE.STD_LOGIC_1164.ALL; 
ENTITY REG1 IS 
  PORT(D: IN STD_LOGIC_VECTOR(9 DOWNTO 0); 
       CLK: IN STD_LOGIC; 
       Q: OUT STD_LOGIC_VECTOR(9 DOWNTO 0)); 
END ENTITY REG1; 
ARCHITECTURE ART OF REG1 IS 
  BEGIN 
  PROCESS(CLK) IS 
    BEGIN 
    IF(CLK'EVENT AND CLK='1')THEN 
      Q<=D; 
    END IF; 
   END PROCESS; 
END ARCHITECTURE ART;