www.pudn.com > multiprocessor.rar > nios.ptf.pre_generation_ptf
SYSTEM nios
{
#
# Generated by: com.altera.sopcmodel.ensemble.EnsembleGeneratePTF
# Date: 2008.01.03.23:53:45
#
# clock_source "clk"
# altera_avalon_new_sdram_controller "sdram"
# altera_avalon_tri_state_bridge "tristate_bridge"
# altera_avalon_cfi_flash "cfi_flash"
# altera_avalon_pio "pio_led"
# altera_avalon_sysid "sysid"
# altera_avalon_jtag_uart "jtag_uart"
# altera_nios2 "cpu2"
# altera_nios2 "cpu1"
# altera_avalon_pio "pio_led2"
# altera_avalon_onchip_memory2 "message_buff_mutex"
# altera_avalon_mutex "mutex"
#
# Contains 34 connections.
#
System_Wizard_Version = "7.2";
Builder_Application = "sopc_builder_ca";
#. values for Builder_Application are:
#. sopc_builder_preview --> 6.1p, 7.0p prerelease versions
#. sopc_builder_ca --> 7.1 and later
#. (missing) --> 6.0 or earlier
WIZARD_SCRIPT_ARGUMENTS
{
hdl_language = "verilog";
device_family = "CYCLONEII";
device_family_id = "CYCLONEII";
generate_sdk = "0";
do_build_sim = "0";
hardcopy_compatible = "0";
CLOCKS
{
CLOCK clk
{
frequency = "50000000";
source = "External";
Is_Clock_Source = "0";
display_name = "clk";
pipeline = "0";
clock_module_connection_point_for_c2h = "clk.clk";
}
}
}
MODULE sdram
{
SLAVE s1
{
PORT_WIRING
{
PORT clk
{
type = "clk";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT reset_n
{
type = "reset_n";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT az_addr
{
type = "address";
width = "22";
direction = "input";
Is_Enabled = "1";
}
PORT az_be_n
{
type = "byteenable_n";
width = "2";
direction = "input";
Is_Enabled = "1";
}
PORT az_cs
{
type = "chipselect";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT az_data
{
type = "writedata";
width = "16";
direction = "input";
Is_Enabled = "1";
}
PORT az_rd_n
{
type = "read_n";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT az_wr_n
{
type = "write_n";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT za_data
{
type = "readdata";
width = "16";
direction = "output";
Is_Enabled = "1";
}
PORT za_valid
{
type = "readdatavalid";
width = "1";
direction = "output";
Is_Enabled = "1";
}
PORT za_waitrequest
{
type = "waitrequest";
width = "1";
direction = "output";
Is_Enabled = "1";
}
}
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Read_Wait_States = "peripheral_controlled";
Write_Wait_States = "peripheral_controlled";
Hold_Time = "0cycles";
Setup_Time = "0cycles";
Is_Printable_Device = "0";
Address_Alignment = "dynamic";
Well_Behaved_Waitrequest = "0";
Is_Nonvolatile_Storage = "0";
Address_Span = "8388608";
Read_Latency = "0";
Is_Memory_Device = "1";
Maximum_Pending_Read_Transactions = "7";
Minimum_Uninterrupted_Run_Length = "1";
Accepts_Internal_Connections = "1";
Write_Latency = "0";
Is_Flash = "0";
Data_Width = "16";
Address_Width = "22";
Maximum_Burst_Size = "1";
Register_Incoming_Signals = "0";
Register_Outgoing_Signals = "0";
Interleave_Bursts = "0";
Linewrap_Bursts = "0";
Burst_On_Burst_Boundaries_Only = "0";
Always_Burst_Max_Burst = "0";
Is_Big_Endian = "0";
Is_Enabled = "1";
MASTERED_BY cpu2/instruction_master
{
priority = "1";
Offset_Address = "0x01000000";
}
MASTERED_BY cpu2/data_master
{
priority = "1";
Offset_Address = "0x01000000";
}
MASTERED_BY cpu1/instruction_master
{
priority = "1";
Offset_Address = "0x01000000";
}
MASTERED_BY cpu1/data_master
{
priority = "1";
Offset_Address = "0x01000000";
}
Base_Address = "0x01000000";
}
}
PORT_WIRING
{
PORT zs_addr
{
type = "zs_addr";
width = "12";
direction = "output";
Is_Enabled = "1";
}
PORT zs_ba
{
type = "zs_ba";
width = "2";
direction = "output";
Is_Enabled = "1";
}
PORT zs_cas_n
{
type = "zs_cas_n";
width = "1";
direction = "output";
Is_Enabled = "1";
}
PORT zs_cke
{
type = "zs_cke";
width = "1";
direction = "output";
Is_Enabled = "1";
}
PORT zs_cs_n
{
type = "zs_cs_n";
width = "1";
direction = "output";
Is_Enabled = "1";
}
PORT zs_dq
{
type = "zs_dq";
width = "16";
direction = "output";
Is_Enabled = "1";
}
PORT zs_dqm
{
type = "zs_dqm";
width = "2";
direction = "output";
Is_Enabled = "1";
}
PORT zs_ras_n
{
type = "zs_ras_n";
width = "1";
direction = "output";
Is_Enabled = "1";
}
PORT zs_we_n
{
type = "zs_we_n";
width = "1";
direction = "output";
Is_Enabled = "1";
}
}
iss_model_name = "altera_memory";
WIZARD_SCRIPT_ARGUMENTS
{
register_data_in = "1";
sim_model_base = "1";
sdram_data_width = "16";
sdram_addr_width = "12";
sdram_row_width = "12";
sdram_col_width = "8";
sdram_num_chipselects = "1";
sdram_num_banks = "4";
refresh_period = "15.625";
powerup_delay = "100.0";
cas_latency = "3";
t_rfc = "70.0";
t_rp = "20.0";
t_mrd = "3";
t_rcd = "20.0";
t_ac = "5.5";
t_wr = "14.0";
init_refresh_commands = "2";
init_nop_delay = "0.0";
shared_data = "0";
sdram_bank_width = "2";
tristate_bridge_slave = "";
}
SIMULATION
{
DISPLAY
{
SIGNAL a
{
name = "az_addr";
radix = "hexadecimal";
}
SIGNAL b
{
name = "az_be_n";
}
SIGNAL c
{
name = "az_cs";
}
SIGNAL d
{
name = "az_data";
radix = "hexadecimal";
}
SIGNAL e
{
name = "az_rd_n";
}
SIGNAL f
{
name = "az_wr_n";
}
SIGNAL h
{
name = "za_data";
radix = "hexadecimal";
}
SIGNAL i
{
name = "za_valid";
}
SIGNAL j
{
name = "za_waitrequest";
}
SIGNAL l
{
name = "CODE";
radix = "ascii";
}
}
}
SYSTEM_BUILDER_INFO
{
Instantiate_In_System_Module = "1";
Is_Enabled = "1";
Default_Module_Name = "sdram";
Top_Level_Ports_Are_Enumerated = "1";
Clock_Source = "clk";
Has_Clock = "1";
}
class = "altera_avalon_new_sdram_controller";
class_version = "7.2";
}
MODULE tristate_bridge
{
SLAVE avalon_slave
{
PORT_WIRING
{
}
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Write_Wait_States = "0cycles";
Read_Wait_States = "1cycles";
Hold_Time = "0cycles";
Setup_Time = "0cycles";
Is_Printable_Device = "0";
Address_Alignment = "dynamic";
Well_Behaved_Waitrequest = "0";
Is_Nonvolatile_Storage = "0";
Address_Span = "1";
Read_Latency = "0";
Is_Memory_Device = "0";
Maximum_Pending_Read_Transactions = "0";
Minimum_Uninterrupted_Run_Length = "1";
Accepts_Internal_Connections = "1";
Write_Latency = "0";
Is_Flash = "0";
Maximum_Burst_Size = "1";
Register_Incoming_Signals = "1";
Register_Outgoing_Signals = "1";
Interleave_Bursts = "0";
Linewrap_Bursts = "0";
Burst_On_Burst_Boundaries_Only = "0";
Always_Burst_Max_Burst = "0";
Is_Big_Endian = "0";
Is_Enabled = "1";
MASTERED_BY cpu2/instruction_master
{
priority = "1";
Offset_Address = "0x00000000";
}
MASTERED_BY cpu2/data_master
{
priority = "1";
Offset_Address = "0x00000000";
}
MASTERED_BY cpu1/instruction_master
{
priority = "1";
Offset_Address = "0x00000000";
}
MASTERED_BY cpu1/data_master
{
priority = "1";
Offset_Address = "0x00000000";
}
}
}
MASTER tristate_master
{
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon_tristate";
Is_Asynchronous = "0";
DBS_Big_Endian = "0";
Adapts_To = "";
Maximum_Burst_Size = "1";
Register_Incoming_Signals = "0";
Register_Outgoing_Signals = "0";
Interleave_Bursts = "0";
Linewrap_Bursts = "0";
Burst_On_Burst_Boundaries_Only = "0";
Always_Burst_Max_Burst = "0";
Is_Big_Endian = "0";
Is_Enabled = "1";
}
PORT_WIRING
{
}
MEMORY_MAP
{
Entry cfi_flash/s1
{
address = "0x01800000";
span = "0x00800000";
}
}
}
WIZARD_SCRIPT_ARGUMENTS
{
}
class = "altera_avalon_tri_state_bridge";
class_version = "7.2";
SYSTEM_BUILDER_INFO
{
Is_Enabled = "1";
Clock_Source = "clk";
Has_Clock = "1";
}
}
MODULE cfi_flash
{
SLAVE s1
{
PORT_WIRING
{
PORT data
{
type = "data";
width = "8";
direction = "inout";
Is_Enabled = "1";
is_shared = "0";
}
PORT address
{
type = "address";
width = "23";
direction = "input";
Is_Enabled = "1";
is_shared = "0";
}
PORT read_n
{
type = "read_n";
width = "1";
direction = "input";
Is_Enabled = "1";
is_shared = "0";
}
PORT write_n
{
type = "write_n";
width = "1";
direction = "input";
Is_Enabled = "1";
is_shared = "0";
}
PORT select_n
{
type = "chipselect_n";
width = "1";
direction = "input";
Is_Enabled = "1";
is_shared = "0";
}
}
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon_tristate";
Write_Wait_States = "120ns";
Read_Wait_States = "120ns";
Hold_Time = "40ns";
Setup_Time = "40ns";
Is_Printable_Device = "0";
Address_Alignment = "dynamic";
Well_Behaved_Waitrequest = "0";
Is_Nonvolatile_Storage = "1";
Address_Span = "8388608";
Read_Latency = "0";
Is_Memory_Device = "1";
Maximum_Pending_Read_Transactions = "0";
Minimum_Uninterrupted_Run_Length = "1";
Accepts_Internal_Connections = "1";
Write_Latency = "0";
Is_Flash = "1";
Active_CS_Through_Read_Latency = "0";
Data_Width = "8";
Address_Width = "23";
Maximum_Burst_Size = "1";
Register_Incoming_Signals = "0";
Register_Outgoing_Signals = "0";
Interleave_Bursts = "0";
Linewrap_Bursts = "0";
Burst_On_Burst_Boundaries_Only = "0";
Always_Burst_Max_Burst = "0";
Is_Big_Endian = "0";
Is_Enabled = "1";
MASTERED_BY tristate_bridge/tristate_master
{
priority = "1";
Offset_Address = "0x01800000";
}
Base_Address = "0x01800000";
}
}
WIZARD_SCRIPT_ARGUMENTS
{
Setup_Value = "40";
Wait_Value = "120";
Hold_Value = "40";
Timing_Units = "ns";
Unit_Multiplier = "1";
Size = "8388608";
}
SYSTEM_BUILDER_INFO
{
Simulation_Num_Lanes = "1";
Is_Enabled = "1";
Clock_Source = "clk";
Has_Clock = "1";
}
class = "altera_avalon_cfi_flash";
class_version = "7.2";
}
MODULE pio_led
{
SLAVE s1
{
PORT_WIRING
{
PORT clk
{
type = "clk";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT reset_n
{
type = "reset_n";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT address
{
type = "address";
width = "2";
direction = "input";
Is_Enabled = "1";
}
PORT write_n
{
type = "write_n";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT writedata
{
type = "writedata";
width = "2";
direction = "input";
Is_Enabled = "1";
}
PORT chipselect
{
type = "chipselect";
width = "1";
direction = "input";
Is_Enabled = "1";
}
}
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Write_Wait_States = "0cycles";
Read_Wait_States = "1cycles";
Hold_Time = "0cycles";
Setup_Time = "0cycles";
Is_Printable_Device = "0";
Address_Alignment = "native";
Well_Behaved_Waitrequest = "0";
Is_Nonvolatile_Storage = "0";
Read_Latency = "0";
Is_Memory_Device = "0";
Maximum_Pending_Read_Transactions = "0";
Minimum_Uninterrupted_Run_Length = "1";
Accepts_Internal_Connections = "1";
Write_Latency = "0";
Is_Flash = "0";
Data_Width = "2";
Address_Width = "2";
Maximum_Burst_Size = "1";
Register_Incoming_Signals = "0";
Register_Outgoing_Signals = "0";
Interleave_Bursts = "0";
Linewrap_Bursts = "0";
Burst_On_Burst_Boundaries_Only = "0";
Always_Burst_Max_Burst = "0";
Is_Big_Endian = "0";
Is_Enabled = "1";
MASTERED_BY cpu1/data_master
{
priority = "1";
Offset_Address = "0x00001000";
}
Base_Address = "0x00001000";
}
}
PORT_WIRING
{
PORT out_port
{
type = "export";
width = "2";
direction = "output";
Is_Enabled = "1";
}
}
class = "altera_avalon_pio";
class_version = "7.2";
SYSTEM_BUILDER_INFO
{
Is_Enabled = "1";
Instantiate_In_System_Module = "1";
Wire_Test_Bench_Values = "1";
Top_Level_Ports_Are_Enumerated = "1";
Clock_Source = "clk";
Has_Clock = "1";
}
WIZARD_SCRIPT_ARGUMENTS
{
Do_Test_Bench_Wiring = "0";
Driven_Sim_Value = "0";
has_tri = "0";
has_out = "1";
has_in = "0";
capture = "0";
Data_Width = "2";
edge_type = "NONE";
irq_type = "NONE";
bit_clearing_edge_register = "0";
}
}
MODULE sysid
{
SLAVE control_slave
{
PORT_WIRING
{
PORT clock
{
type = "clk";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT reset_n
{
type = "reset_n";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT address
{
type = "address";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT readdata
{
type = "readdata";
width = "32";
direction = "output";
Is_Enabled = "1";
}
}
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Write_Wait_States = "0cycles";
Read_Wait_States = "1cycles";
Hold_Time = "0cycles";
Setup_Time = "0cycles";
Is_Printable_Device = "0";
Address_Alignment = "native";
Well_Behaved_Waitrequest = "0";
Is_Nonvolatile_Storage = "0";
Read_Latency = "0";
Is_Memory_Device = "0";
Maximum_Pending_Read_Transactions = "0";
Minimum_Uninterrupted_Run_Length = "1";
Accepts_Internal_Connections = "1";
Write_Latency = "0";
Is_Flash = "0";
Data_Width = "32";
Address_Width = "1";
Maximum_Burst_Size = "1";
Register_Incoming_Signals = "0";
Register_Outgoing_Signals = "0";
Interleave_Bursts = "0";
Linewrap_Bursts = "0";
Burst_On_Burst_Boundaries_Only = "0";
Always_Burst_Max_Burst = "0";
Is_Big_Endian = "0";
Is_Enabled = "1";
MASTERED_BY cpu2/data_master
{
priority = "1";
Offset_Address = "0x02001810";
}
MASTERED_BY cpu1/data_master
{
priority = "1";
Offset_Address = "0x02001810";
}
Base_Address = "0x02001810";
}
}
class = "altera_avalon_sysid";
class_version = "7.2";
SYSTEM_BUILDER_INFO
{
Date_Modified = "";
Is_Enabled = "1";
Instantiate_In_System_Module = "1";
Fixed_Module_Name = "sysid";
Top_Level_Ports_Are_Enumerated = "1";
Clock_Source = "clk";
Has_Clock = "1";
}
WIZARD_SCRIPT_ARGUMENTS
{
id = "1231239703";
timestamp = "1199375215";
regenerate_values = "0";
}
}
MODULE jtag_uart
{
SLAVE avalon_jtag_slave
{
PORT_WIRING
{
PORT clk
{
type = "clk";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT reset_n
{
type = "reset_n";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT av_irq
{
type = "irq";
width = "1";
direction = "output";
Is_Enabled = "1";
}
PORT av_chipselect
{
type = "chipselect";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT av_address
{
type = "address";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT av_read_n
{
type = "read_n";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT av_readdata
{
type = "readdata";
width = "32";
direction = "output";
Is_Enabled = "1";
}
PORT av_write_n
{
type = "write_n";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT av_writedata
{
type = "writedata";
width = "32";
direction = "input";
Is_Enabled = "1";
}
PORT av_waitrequest
{
type = "waitrequest";
width = "1";
direction = "output";
Is_Enabled = "1";
}
PORT dataavailable
{
type = "dataavailable";
width = "1";
direction = "output";
Is_Enabled = "1";
}
PORT readyfordata
{
type = "readyfordata";
width = "1";
direction = "output";
Is_Enabled = "1";
}
}
SYSTEM_BUILDER_INFO
{
Has_IRQ = "1";
Bus_Type = "avalon";
Read_Wait_States = "peripheral_controlled";
Write_Wait_States = "peripheral_controlled";
Hold_Time = "0cycles";
Setup_Time = "0cycles";
Is_Printable_Device = "1";
Address_Alignment = "native";
Well_Behaved_Waitrequest = "0";
Is_Nonvolatile_Storage = "0";
Read_Latency = "0";
Is_Memory_Device = "0";
Maximum_Pending_Read_Transactions = "0";
Minimum_Uninterrupted_Run_Length = "1";
Accepts_Internal_Connections = "1";
Write_Latency = "0";
Is_Flash = "0";
Data_Width = "32";
Address_Width = "1";
Maximum_Burst_Size = "1";
Register_Incoming_Signals = "0";
Register_Outgoing_Signals = "0";
Interleave_Bursts = "0";
Linewrap_Bursts = "0";
Burst_On_Burst_Boundaries_Only = "0";
Always_Burst_Max_Burst = "0";
Is_Big_Endian = "0";
Is_Enabled = "1";
JTAG_Hub_Base_Id = "262254";
JTAG_Hub_Instance_Id = "0";
Connection_Limit = "1";
IRQ_MASTER cpu1/data_master
{
IRQ_Number = "1";
}
MASTERED_BY cpu1/data_master
{
priority = "1";
Offset_Address = "0x00001010";
}
Base_Address = "0x00001010";
}
}
class = "altera_avalon_jtag_uart";
class_version = "7.2";
iss_model_name = "altera_avalon_jtag_uart";
WIZARD_SCRIPT_ARGUMENTS
{
write_depth = "64";
read_depth = "64";
write_threshold = "8";
read_threshold = "8";
read_char_stream = "";
showascii = "1";
read_le = "0";
write_le = "0";
altera_show_unreleased_jtag_uart_features = "0";
}
SIMULATION
{
DISPLAY
{
SIGNAL av_chipselect
{
name = "av_chipselect";
}
SIGNAL av_address
{
name = "av_address";
}
SIGNAL av_read_n
{
name = "av_read_n";
}
SIGNAL av_readdata
{
name = "av_readdata";
radix = "hexadecimal";
}
SIGNAL av_write_n
{
name = "av_write_n";
}
SIGNAL av_writedata
{
name = "av_writedata";
radix = "hexadecimal";
}
SIGNAL av_waitrequest
{
name = "av_waitrequest";
}
SIGNAL dataavailable
{
name = "dataavailable";
}
SIGNAL readyfordata
{
name = "readyfordata";
}
}
INTERACTIVE_IN drive
{
enable = "0";
file = "_input_data_stream.dat";
mutex = "_input_data_mutex.dat";
log = "_in.log";
rate = "100";
signals = "temp,list";
exe = "nios2-terminal";
}
INTERACTIVE_OUT log
{
enable = "1";
exe = "perl -- atail-f.pl";
file = "_output_stream.dat";
radix = "ascii";
signals = "temp,list";
}
}
SYSTEM_BUILDER_INFO
{
Is_Enabled = "1";
Clock_Source = "clk";
Has_Clock = "1";
}
}
MODULE cpu2
{
MASTER instruction_master
{
PORT_WIRING
{
PORT clk
{
type = "clk";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT reset_n
{
type = "reset_n";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT i_address
{
type = "address";
width = "26";
direction = "output";
Is_Enabled = "1";
}
PORT i_read
{
type = "read";
width = "1";
direction = "output";
Is_Enabled = "1";
}
PORT i_readdata
{
type = "readdata";
width = "32";
direction = "input";
Is_Enabled = "1";
}
PORT i_readdatavalid
{
type = "readdatavalid";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT i_waitrequest
{
type = "waitrequest";
width = "1";
direction = "input";
Is_Enabled = "1";
}
}
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Is_Asynchronous = "0";
DBS_Big_Endian = "0";
Adapts_To = "";
Do_Stream_Reads = "0";
Do_Stream_Writes = "0";
Max_Address_Width = "32";
Data_Width = "32";
Address_Width = "26";
Maximum_Burst_Size = "1";
Register_Incoming_Signals = "0";
Register_Outgoing_Signals = "0";
Interleave_Bursts = "0";
Linewrap_Bursts = "0";
Burst_On_Burst_Boundaries_Only = "0";
Always_Burst_Max_Burst = "0";
Is_Big_Endian = "0";
Is_Enabled = "1";
Is_Instruction_Master = "1";
}
MEMORY_MAP
{
Entry cpu2/jtag_debug_module
{
address = "0x02000800";
span = "0x00000800";
}
Entry sdram/s1
{
address = "0x01000000";
span = "0x00800000";
}
Entry cfi_flash/s1
{
address = "0x01800000";
span = "0x00800000";
}
}
}
MASTER custom_instruction_master
{
SYSTEM_BUILDER_INFO
{
Bus_Type = "nios_custom_instruction";
Data_Width = "32";
Address_Width = "8";
Is_Custom_Instruction = "1";
Is_Enabled = "0";
Max_Address_Width = "8";
}
PORT_WIRING
{
PORT dataa
{
type = "dataa";
width = "32";
direction = "output";
}
PORT datab
{
type = "datab";
width = "32";
direction = "output";
}
PORT result
{
type = "result";
width = "32";
direction = "input";
}
PORT clk_en
{
type = "clk_en";
width = "1";
direction = "output";
}
PORT reset
{
type = "reset";
width = "1";
direction = "output";
}
PORT start
{
type = "start";
width = "1";
direction = "output";
}
PORT done
{
type = "done";
width = "1";
direction = "input";
}
PORT n
{
type = "n";
width = "8";
direction = "output";
}
PORT a
{
type = "a";
width = "5";
direction = "output";
}
PORT b
{
type = "b";
width = "5";
direction = "output";
}
PORT c
{
type = "c";
width = "5";
direction = "output";
}
PORT readra
{
type = "readra";
width = "1";
direction = "output";
}
PORT readrb
{
type = "readrb";
width = "1";
direction = "output";
}
PORT writerc
{
type = "writerc";
width = "1";
direction = "output";
}
}
}
SLAVE jtag_debug_module
{
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Write_Wait_States = "0cycles";
Read_Wait_States = "1cycles";
Hold_Time = "0cycles";
Setup_Time = "0cycles";
Is_Printable_Device = "0";
Address_Alignment = "dynamic";
Well_Behaved_Waitrequest = "0";
Is_Nonvolatile_Storage = "0";
Address_Span = "2048";
Read_Latency = "0";
Is_Memory_Device = "1";
Maximum_Pending_Read_Transactions = "0";
Minimum_Uninterrupted_Run_Length = "1";
Accepts_Internal_Connections = "1";
Write_Latency = "0";
Is_Flash = "0";
Data_Width = "32";
Address_Width = "9";
Maximum_Burst_Size = "1";
Register_Incoming_Signals = "0";
Register_Outgoing_Signals = "0";
Interleave_Bursts = "0";
Linewrap_Bursts = "0";
Burst_On_Burst_Boundaries_Only = "0";
Always_Burst_Max_Burst = "0";
Is_Big_Endian = "0";
Is_Enabled = "1";
Accepts_External_Connections = "1";
Requires_Internal_Connections = "";
MASTERED_BY cpu2/instruction_master
{
priority = "1";
Offset_Address = "0x02000800";
}
MASTERED_BY cpu2/data_master
{
priority = "1";
Offset_Address = "0x02000800";
}
Base_Address = "0x02000800";
}
PORT_WIRING
{
PORT jtag_debug_module_address
{
type = "address";
width = "9";
direction = "input";
Is_Enabled = "1";
}
PORT jtag_debug_module_begintransfer
{
type = "begintransfer";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT jtag_debug_module_byteenable
{
type = "byteenable";
width = "4";
direction = "input";
Is_Enabled = "1";
}
PORT jtag_debug_module_clk
{
type = "clk";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT jtag_debug_module_debugaccess
{
type = "debugaccess";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT jtag_debug_module_readdata
{
type = "readdata";
width = "32";
direction = "output";
Is_Enabled = "1";
}
PORT jtag_debug_module_reset
{
type = "reset";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT jtag_debug_module_resetrequest
{
type = "resetrequest";
width = "1";
direction = "output";
Is_Enabled = "1";
}
PORT jtag_debug_module_select
{
type = "chipselect";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT jtag_debug_module_write
{
type = "write";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT jtag_debug_module_writedata
{
type = "writedata";
width = "32";
direction = "input";
Is_Enabled = "1";
}
}
}
MASTER data_master
{
SYSTEM_BUILDER_INFO
{
Has_IRQ = "1";
Irq_Scheme = "individual_requests";
Bus_Type = "avalon";
Is_Asynchronous = "0";
DBS_Big_Endian = "0";
Adapts_To = "";
Do_Stream_Reads = "0";
Do_Stream_Writes = "0";
Max_Address_Width = "32";
Data_Width = "32";
Address_Width = "26";
Maximum_Burst_Size = "1";
Register_Incoming_Signals = "0";
Register_Outgoing_Signals = "0";
Interleave_Bursts = "0";
Linewrap_Bursts = "0";
Burst_On_Burst_Boundaries_Only = "0";
Always_Burst_Max_Burst = "0";
Is_Big_Endian = "0";
Is_Enabled = "1";
Is_Data_Master = "1";
}
PORT_WIRING
{
PORT d_irq
{
type = "irq";
width = "32";
direction = "input";
Is_Enabled = "1";
}
PORT d_address
{
type = "address";
width = "26";
direction = "output";
Is_Enabled = "1";
}
PORT d_byteenable
{
type = "byteenable";
width = "4";
direction = "output";
Is_Enabled = "1";
}
PORT d_read
{
type = "read";
width = "1";
direction = "output";
Is_Enabled = "1";
}
PORT d_readdata
{
type = "readdata";
width = "32";
direction = "input";
Is_Enabled = "1";
}
PORT d_readdatavalid
{
type = "readdatavalid";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT d_waitrequest
{
type = "waitrequest";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT d_write
{
type = "write";
width = "1";
direction = "output";
Is_Enabled = "1";
}
PORT d_writedata
{
type = "writedata";
width = "32";
direction = "output";
Is_Enabled = "1";
}
PORT jtag_debug_module_debugaccess_to_roms
{
type = "debugaccess";
width = "1";
direction = "output";
Is_Enabled = "1";
}
}
MEMORY_MAP
{
Entry cpu2/jtag_debug_module
{
address = "0x02000800";
span = "0x00000800";
}
Entry sdram/s1
{
address = "0x01000000";
span = "0x00800000";
}
Entry cfi_flash/s1
{
address = "0x01800000";
span = "0x00800000";
}
Entry sysid/control_slave
{
address = "0x02001810";
span = "0x00000008";
}
Entry pio_led2/s1
{
address = "0x02001800";
span = "0x00000010";
}
Entry message_buff_mutex/s1
{
address = "0x02001000";
span = "0x00000800";
}
Entry mutex/s1
{
address = "0x02001818";
span = "0x00000008";
}
}
}
WIZARD_SCRIPT_ARGUMENTS
{
cache_has_dcache = "0";
cache_dcache_size = "0";
cache_dcache_line_size = "0";
cache_dcache_bursts = "0";
cache_dcache_ram_block_type = "AUTO";
num_tightly_coupled_data_masters = "0";
gui_num_tightly_coupled_data_masters = "0";
gui_include_tightly_coupled_data_masters = "0";
gui_omit_avalon_data_master = "0";
cache_has_icache = "0";
cache_icache_size = "0";
cache_icache_line_size = "0";
cache_icache_ram_block_type = "AUTO";
cache_icache_bursts = "0";
num_tightly_coupled_instruction_masters = "0";
gui_num_tightly_coupled_instruction_masters = "0";
gui_include_tightly_coupled_instruction_masters = "0";
debug_level = "2";
include_oci = "1";
oci_sbi_enabled = "1";
oci_num_xbrk = "0";
oci_num_dbrk = "0";
oci_dbrk_trace = "0";
oci_dbrk_pairs = "0";
oci_onchip_trace = "0";
oci_offchip_trace = "0";
oci_data_trace = "0";
include_third_party_debug_port = "0";
oci_trace_addr_width = "7";
oci_trigger_arming = "1";
oci_debugreq_signals = "0";
oci_embedded_pll = "1";
oci_num_pm = "0";
oci_pm_width = "32";
performance_counters_present = "0";
performance_counters_width = "32";
always_encrypt = "1";
debug_simgen = "0";
activate_model_checker = "0";
activate_test_end_checker = "0";
activate_trace = "1";
activate_monitors = "1";
clear_x_bits_ld_non_bypass = "1";
bit_31_bypass_dcache = "1";
always_bypass_dcache = "0";
hdl_sim_caches_cleared = "1";
hbreak_test = "0";
allow_full_address_range = "0";
branch_prediction_type = "Static";
bht_ptr_sz = "8";
bht_index_pc_only = "0";
gui_branch_prediction_type = "Automatic";
full_waveform_signals = "0";
export_pcb = "0";
avalon_debug_port_present = "0";
gui_illegal_instructions_trap = "0";
gui_illegal_memory_access_detection = "0";
illegal_mem_exc = "0";
slave_access_error_exc = "0";
division_error_exc = "0";
gui_mmu_present = "0";
process_id_num_bits = "10";
dtlb_ptr_sz = "7";
itlb_ptr_sz = "7";
dtlb_num_ways = "4";
itlb_num_ways = "4";
udtlb_num_entries = "6";
uitlb_num_entries = "4";
fast_tlb_miss_exc_slave = "";
fast_tlb_miss_exc_offset = "0x00000000";
hardware_divide_present = "0";
gui_hardware_divide_setting = "0";
hardware_multiply_present = "0";
hardware_multiply_impl = "no_mul";
shift_rot_impl = "small_le_shift";
gui_hardware_multiply_setting = "no_mul_small_le_shift";
reset_slave = "cfi_flash/s1";
break_slave = "cpu2/jtag_debug_module";
exc_slave = "sdram/s1";
reset_offset = "0x00000000";
break_offset = "0x00000020";
exc_offset = "0x00000020";
cpu_reset = "0";
CPU_Implementation = "tiny";
cpu_selection = "e";
device_family_id = "CYCLONEII";
address_stall_present = "1";
dsp_block_supports_shift = "0";
mrams_present = "0";
do_generate = "1";
cpuid_value = "1";
cpuid_sz = "1";
dont_overwrite_cpuid = "1";
allow_legacy_sdk = "1";
legacy_sdk_support = "1";
inst_addr_width = "26";
data_addr_width = "26";
}
class = "altera_nios2";
class_version = "7.2";
SYSTEM_BUILDER_INFO
{
Is_Enabled = "1";
Clock_Source = "clk";
Has_Clock = "1";
}
}
MODULE cpu1
{
MASTER instruction_master
{
PORT_WIRING
{
PORT clk
{
type = "clk";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT reset_n
{
type = "reset_n";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT i_address
{
type = "address";
width = "25";
direction = "output";
Is_Enabled = "1";
}
PORT i_read
{
type = "read";
width = "1";
direction = "output";
Is_Enabled = "1";
}
PORT i_readdata
{
type = "readdata";
width = "32";
direction = "input";
Is_Enabled = "1";
}
PORT i_readdatavalid
{
type = "readdatavalid";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT i_waitrequest
{
type = "waitrequest";
width = "1";
direction = "input";
Is_Enabled = "1";
}
}
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Is_Asynchronous = "0";
DBS_Big_Endian = "0";
Adapts_To = "";
Do_Stream_Reads = "0";
Do_Stream_Writes = "0";
Max_Address_Width = "32";
Data_Width = "32";
Address_Width = "25";
Maximum_Burst_Size = "1";
Register_Incoming_Signals = "0";
Register_Outgoing_Signals = "0";
Interleave_Bursts = "0";
Linewrap_Bursts = "0";
Burst_On_Burst_Boundaries_Only = "0";
Always_Burst_Max_Burst = "0";
Is_Big_Endian = "0";
Is_Enabled = "1";
Is_Instruction_Master = "1";
}
MEMORY_MAP
{
Entry cpu1/jtag_debug_module
{
address = "0x00000800";
span = "0x00000800";
}
Entry sdram/s1
{
address = "0x01000000";
span = "0x00800000";
}
Entry cfi_flash/s1
{
address = "0x01800000";
span = "0x00800000";
}
}
}
MASTER custom_instruction_master
{
SYSTEM_BUILDER_INFO
{
Bus_Type = "nios_custom_instruction";
Data_Width = "32";
Address_Width = "8";
Is_Custom_Instruction = "1";
Is_Enabled = "0";
Max_Address_Width = "8";
}
PORT_WIRING
{
PORT dataa
{
type = "dataa";
width = "32";
direction = "output";
}
PORT datab
{
type = "datab";
width = "32";
direction = "output";
}
PORT result
{
type = "result";
width = "32";
direction = "input";
}
PORT clk_en
{
type = "clk_en";
width = "1";
direction = "output";
}
PORT reset
{
type = "reset";
width = "1";
direction = "output";
}
PORT start
{
type = "start";
width = "1";
direction = "output";
}
PORT done
{
type = "done";
width = "1";
direction = "input";
}
PORT n
{
type = "n";
width = "8";
direction = "output";
}
PORT a
{
type = "a";
width = "5";
direction = "output";
}
PORT b
{
type = "b";
width = "5";
direction = "output";
}
PORT c
{
type = "c";
width = "5";
direction = "output";
}
PORT readra
{
type = "readra";
width = "1";
direction = "output";
}
PORT readrb
{
type = "readrb";
width = "1";
direction = "output";
}
PORT writerc
{
type = "writerc";
width = "1";
direction = "output";
}
}
}
SLAVE jtag_debug_module
{
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Write_Wait_States = "0cycles";
Read_Wait_States = "1cycles";
Hold_Time = "0cycles";
Setup_Time = "0cycles";
Is_Printable_Device = "0";
Address_Alignment = "dynamic";
Well_Behaved_Waitrequest = "0";
Is_Nonvolatile_Storage = "0";
Address_Span = "2048";
Read_Latency = "0";
Is_Memory_Device = "1";
Maximum_Pending_Read_Transactions = "0";
Minimum_Uninterrupted_Run_Length = "1";
Accepts_Internal_Connections = "1";
Write_Latency = "0";
Is_Flash = "0";
Data_Width = "32";
Address_Width = "9";
Maximum_Burst_Size = "1";
Register_Incoming_Signals = "0";
Register_Outgoing_Signals = "0";
Interleave_Bursts = "0";
Linewrap_Bursts = "0";
Burst_On_Burst_Boundaries_Only = "0";
Always_Burst_Max_Burst = "0";
Is_Big_Endian = "0";
Is_Enabled = "1";
Accepts_External_Connections = "1";
Requires_Internal_Connections = "";
MASTERED_BY cpu1/instruction_master
{
priority = "1";
Offset_Address = "0x00000800";
}
MASTERED_BY cpu1/data_master
{
priority = "1";
Offset_Address = "0x00000800";
}
Base_Address = "0x00000800";
}
PORT_WIRING
{
PORT jtag_debug_module_address
{
type = "address";
width = "9";
direction = "input";
Is_Enabled = "1";
}
PORT jtag_debug_module_begintransfer
{
type = "begintransfer";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT jtag_debug_module_byteenable
{
type = "byteenable";
width = "4";
direction = "input";
Is_Enabled = "1";
}
PORT jtag_debug_module_clk
{
type = "clk";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT jtag_debug_module_debugaccess
{
type = "debugaccess";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT jtag_debug_module_readdata
{
type = "readdata";
width = "32";
direction = "output";
Is_Enabled = "1";
}
PORT jtag_debug_module_reset
{
type = "reset";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT jtag_debug_module_resetrequest
{
type = "resetrequest";
width = "1";
direction = "output";
Is_Enabled = "1";
}
PORT jtag_debug_module_select
{
type = "chipselect";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT jtag_debug_module_write
{
type = "write";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT jtag_debug_module_writedata
{
type = "writedata";
width = "32";
direction = "input";
Is_Enabled = "1";
}
}
}
MASTER data_master
{
SYSTEM_BUILDER_INFO
{
Has_IRQ = "1";
Irq_Scheme = "individual_requests";
Bus_Type = "avalon";
Is_Asynchronous = "0";
DBS_Big_Endian = "0";
Adapts_To = "";
Do_Stream_Reads = "0";
Do_Stream_Writes = "0";
Max_Address_Width = "32";
Data_Width = "32";
Address_Width = "26";
Maximum_Burst_Size = "1";
Register_Incoming_Signals = "0";
Register_Outgoing_Signals = "0";
Interleave_Bursts = "0";
Linewrap_Bursts = "0";
Burst_On_Burst_Boundaries_Only = "0";
Always_Burst_Max_Burst = "0";
Is_Big_Endian = "0";
Is_Enabled = "1";
Is_Data_Master = "1";
}
PORT_WIRING
{
PORT d_irq
{
type = "irq";
width = "32";
direction = "input";
Is_Enabled = "1";
}
PORT d_address
{
type = "address";
width = "26";
direction = "output";
Is_Enabled = "1";
}
PORT d_byteenable
{
type = "byteenable";
width = "4";
direction = "output";
Is_Enabled = "1";
}
PORT d_read
{
type = "read";
width = "1";
direction = "output";
Is_Enabled = "1";
}
PORT d_readdata
{
type = "readdata";
width = "32";
direction = "input";
Is_Enabled = "1";
}
PORT d_readdatavalid
{
type = "readdatavalid";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT d_waitrequest
{
type = "waitrequest";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT d_write
{
type = "write";
width = "1";
direction = "output";
Is_Enabled = "1";
}
PORT d_writedata
{
type = "writedata";
width = "32";
direction = "output";
Is_Enabled = "1";
}
PORT jtag_debug_module_debugaccess_to_roms
{
type = "debugaccess";
width = "1";
direction = "output";
Is_Enabled = "1";
}
}
MEMORY_MAP
{
Entry cpu1/jtag_debug_module
{
address = "0x00000800";
span = "0x00000800";
}
Entry sdram/s1
{
address = "0x01000000";
span = "0x00800000";
}
Entry cfi_flash/s1
{
address = "0x01800000";
span = "0x00800000";
}
Entry pio_led/s1
{
address = "0x00001000";
span = "0x00000010";
}
Entry sysid/control_slave
{
address = "0x02001810";
span = "0x00000008";
}
Entry jtag_uart/avalon_jtag_slave
{
address = "0x00001010";
span = "0x00000008";
}
Entry message_buff_mutex/s1
{
address = "0x02001000";
span = "0x00000800";
}
Entry mutex/s1
{
address = "0x02001818";
span = "0x00000008";
}
}
}
WIZARD_SCRIPT_ARGUMENTS
{
cache_has_dcache = "0";
cache_dcache_size = "0";
cache_dcache_line_size = "0";
cache_dcache_bursts = "0";
cache_dcache_ram_block_type = "AUTO";
num_tightly_coupled_data_masters = "0";
gui_num_tightly_coupled_data_masters = "0";
gui_include_tightly_coupled_data_masters = "0";
gui_omit_avalon_data_master = "0";
cache_has_icache = "1";
cache_icache_size = "1024";
cache_icache_line_size = "32";
cache_icache_ram_block_type = "AUTO";
cache_icache_bursts = "0";
num_tightly_coupled_instruction_masters = "0";
gui_num_tightly_coupled_instruction_masters = "0";
gui_include_tightly_coupled_instruction_masters = "0";
debug_level = "2";
include_oci = "1";
oci_sbi_enabled = "1";
oci_num_xbrk = "0";
oci_num_dbrk = "0";
oci_dbrk_trace = "0";
oci_dbrk_pairs = "0";
oci_onchip_trace = "0";
oci_offchip_trace = "0";
oci_data_trace = "0";
include_third_party_debug_port = "0";
oci_trace_addr_width = "7";
oci_trigger_arming = "1";
oci_debugreq_signals = "0";
oci_embedded_pll = "1";
oci_num_pm = "0";
oci_pm_width = "32";
performance_counters_present = "0";
performance_counters_width = "32";
always_encrypt = "1";
debug_simgen = "0";
activate_model_checker = "0";
activate_test_end_checker = "0";
activate_trace = "1";
activate_monitors = "1";
clear_x_bits_ld_non_bypass = "1";
bit_31_bypass_dcache = "1";
always_bypass_dcache = "0";
hdl_sim_caches_cleared = "1";
hbreak_test = "0";
allow_full_address_range = "0";
branch_prediction_type = "Static";
bht_ptr_sz = "8";
bht_index_pc_only = "0";
gui_branch_prediction_type = "Automatic";
full_waveform_signals = "0";
export_pcb = "0";
avalon_debug_port_present = "0";
gui_illegal_instructions_trap = "0";
gui_illegal_memory_access_detection = "0";
illegal_mem_exc = "0";
slave_access_error_exc = "0";
division_error_exc = "0";
gui_mmu_present = "0";
process_id_num_bits = "10";
dtlb_ptr_sz = "7";
itlb_ptr_sz = "7";
dtlb_num_ways = "4";
itlb_num_ways = "4";
udtlb_num_entries = "6";
uitlb_num_entries = "4";
fast_tlb_miss_exc_slave = "";
fast_tlb_miss_exc_offset = "0x00000000";
hardware_divide_present = "0";
gui_hardware_divide_setting = "0";
hardware_multiply_present = "0";
hardware_multiply_impl = "no_mul";
shift_rot_impl = "small_le_shift";
gui_hardware_multiply_setting = "no_mul_small_le_shift";
reset_slave = "cfi_flash/s1";
break_slave = "cpu1/jtag_debug_module";
exc_slave = "sdram/s1";
reset_offset = "0x00200000";
break_offset = "0x00000020";
exc_offset = "0x00200020";
cpu_reset = "0";
CPU_Implementation = "small";
cpu_selection = "s";
device_family_id = "CYCLONEII";
address_stall_present = "1";
dsp_block_supports_shift = "0";
mrams_present = "0";
do_generate = "1";
cpuid_value = "0";
cpuid_sz = "1";
dont_overwrite_cpuid = "1";
allow_legacy_sdk = "1";
legacy_sdk_support = "1";
inst_addr_width = "25";
data_addr_width = "26";
}
class = "altera_nios2";
class_version = "7.2";
SYSTEM_BUILDER_INFO
{
Is_Enabled = "1";
Clock_Source = "clk";
Has_Clock = "1";
}
}
MODULE pio_led2
{
SLAVE s1
{
PORT_WIRING
{
PORT clk
{
type = "clk";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT reset_n
{
type = "reset_n";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT address
{
type = "address";
width = "2";
direction = "input";
Is_Enabled = "1";
}
PORT write_n
{
type = "write_n";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT writedata
{
type = "writedata";
width = "2";
direction = "input";
Is_Enabled = "1";
}
PORT chipselect
{
type = "chipselect";
width = "1";
direction = "input";
Is_Enabled = "1";
}
}
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Write_Wait_States = "0cycles";
Read_Wait_States = "1cycles";
Hold_Time = "0cycles";
Setup_Time = "0cycles";
Is_Printable_Device = "0";
Address_Alignment = "native";
Well_Behaved_Waitrequest = "0";
Is_Nonvolatile_Storage = "0";
Read_Latency = "0";
Is_Memory_Device = "0";
Maximum_Pending_Read_Transactions = "0";
Minimum_Uninterrupted_Run_Length = "1";
Accepts_Internal_Connections = "1";
Write_Latency = "0";
Is_Flash = "0";
Data_Width = "2";
Address_Width = "2";
Maximum_Burst_Size = "1";
Register_Incoming_Signals = "0";
Register_Outgoing_Signals = "0";
Interleave_Bursts = "0";
Linewrap_Bursts = "0";
Burst_On_Burst_Boundaries_Only = "0";
Always_Burst_Max_Burst = "0";
Is_Big_Endian = "0";
Is_Enabled = "1";
MASTERED_BY cpu2/data_master
{
priority = "1";
Offset_Address = "0x02001800";
}
Base_Address = "0x02001800";
}
}
PORT_WIRING
{
PORT out_port
{
type = "export";
width = "2";
direction = "output";
Is_Enabled = "1";
}
}
class = "altera_avalon_pio";
class_version = "7.2";
SYSTEM_BUILDER_INFO
{
Is_Enabled = "1";
Instantiate_In_System_Module = "1";
Wire_Test_Bench_Values = "1";
Top_Level_Ports_Are_Enumerated = "1";
Clock_Source = "clk";
Has_Clock = "1";
}
WIZARD_SCRIPT_ARGUMENTS
{
Do_Test_Bench_Wiring = "0";
Driven_Sim_Value = "0";
has_tri = "0";
has_out = "1";
has_in = "0";
capture = "0";
Data_Width = "2";
edge_type = "NONE";
irq_type = "NONE";
bit_clearing_edge_register = "0";
}
}
MODULE message_buff_mutex
{
SLAVE s1
{
PORT_WIRING
{
PORT clk
{
type = "clk";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT reset_n
{
type = "reset_n";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT address
{
type = "address";
width = "9";
direction = "input";
Is_Enabled = "1";
}
PORT chipselect
{
type = "chipselect";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT clken
{
type = "clken";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT read
{
type = "read";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT readdata
{
type = "readdata";
width = "32";
direction = "output";
Is_Enabled = "1";
}
PORT write
{
type = "write";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT writedata
{
type = "writedata";
width = "32";
direction = "input";
Is_Enabled = "1";
}
PORT debugaccess
{
type = "debugaccess";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT byteenable
{
type = "byteenable";
width = "4";
direction = "input";
Is_Enabled = "1";
}
}
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Write_Wait_States = "0cycles";
Read_Wait_States = "0cycles";
Hold_Time = "0cycles";
Setup_Time = "0cycles";
Is_Printable_Device = "0";
Address_Alignment = "dynamic";
Well_Behaved_Waitrequest = "0";
Is_Nonvolatile_Storage = "0";
Address_Span = "2048";
Read_Latency = "1";
Is_Memory_Device = "1";
Maximum_Pending_Read_Transactions = "0";
Minimum_Uninterrupted_Run_Length = "1";
Accepts_Internal_Connections = "1";
Write_Latency = "0";
Is_Flash = "0";
Data_Width = "32";
Address_Width = "9";
Maximum_Burst_Size = "1";
Register_Incoming_Signals = "0";
Register_Outgoing_Signals = "0";
Interleave_Bursts = "0";
Linewrap_Bursts = "0";
Burst_On_Burst_Boundaries_Only = "0";
Always_Burst_Max_Burst = "0";
Is_Big_Endian = "0";
Is_Enabled = "1";
MASTERED_BY cpu1/data_master
{
priority = "1";
Offset_Address = "0x02001000";
}
MASTERED_BY cpu2/data_master
{
priority = "1";
Offset_Address = "0x02001000";
}
Base_Address = "0x02001000";
}
}
iss_model_name = "altera_memory";
WIZARD_SCRIPT_ARGUMENTS
{
allow_mram_sim_contents_only_file = "0";
ram_block_type = "AUTO";
init_contents_file = "message_buff_mutex";
non_default_init_file_enabled = "0";
gui_ram_block_type = "Automatic";
Writeable = "1";
dual_port = "0";
Size_Value = "2048";
Size_Multiple = "1";
use_shallow_mem_blocks = "0";
init_mem_content = "1";
allow_in_system_memory_content_editor = "0";
instance_id = "NONE";
ignore_auto_block_type_assignment = "1";
}
SIMULATION
{
DISPLAY
{
SIGNAL a
{
name = "chipselect";
conditional = "1";
}
SIGNAL c
{
name = "address";
radix = "hexadecimal";
}
SIGNAL d
{
name = "byteenable";
radix = "binary";
conditional = "1";
}
SIGNAL e
{
name = "readdata";
radix = "hexadecimal";
}
SIGNAL b
{
name = "write";
conditional = "1";
}
SIGNAL f
{
name = "writedata";
radix = "hexadecimal";
conditional = "1";
}
}
}
SYSTEM_BUILDER_INFO
{
Prohibited_Device_Family = "MERCURY, APEX20K, APEX20KE, APEX20KC, APEXII, ACEX1K, FLEX10KE, EXCALIBUR_ARM, MAXII";
Instantiate_In_System_Module = "1";
Is_Enabled = "1";
Default_Module_Name = "onchip_memory";
Top_Level_Ports_Are_Enumerated = "1";
Clock_Source = "clk";
Has_Clock = "1";
}
class = "altera_avalon_onchip_memory2";
class_version = "7.2";
}
MODULE mutex
{
SLAVE s1
{
PORT_WIRING
{
PORT clk
{
type = "clk";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT reset_n
{
type = "reset_n";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT address
{
type = "address";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT chipselect
{
type = "chipselect";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT data_from_cpu
{
type = "writedata";
width = "32";
direction = "input";
Is_Enabled = "1";
}
PORT data_to_cpu
{
type = "readdata";
width = "32";
direction = "output";
Is_Enabled = "1";
}
PORT read
{
type = "read";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT write
{
type = "write";
width = "1";
direction = "input";
Is_Enabled = "1";
}
}
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Write_Wait_States = "0cycles";
Read_Wait_States = "1cycles";
Hold_Time = "0cycles";
Setup_Time = "0cycles";
Is_Printable_Device = "0";
Address_Alignment = "native";
Well_Behaved_Waitrequest = "0";
Is_Nonvolatile_Storage = "0";
Read_Latency = "0";
Is_Memory_Device = "0";
Maximum_Pending_Read_Transactions = "0";
Minimum_Uninterrupted_Run_Length = "1";
Accepts_Internal_Connections = "1";
Write_Latency = "0";
Is_Flash = "0";
Data_Width = "32";
Address_Width = "1";
Maximum_Burst_Size = "1";
Register_Incoming_Signals = "0";
Register_Outgoing_Signals = "0";
Interleave_Bursts = "0";
Linewrap_Bursts = "0";
Burst_On_Burst_Boundaries_Only = "0";
Always_Burst_Max_Burst = "0";
Is_Big_Endian = "0";
Is_Enabled = "1";
MASTERED_BY cpu1/data_master
{
priority = "1";
Offset_Address = "0x02001818";
}
MASTERED_BY cpu2/data_master
{
priority = "1";
Offset_Address = "0x02001818";
}
Base_Address = "0x02001818";
}
}
WIZARD_SCRIPT_ARGUMENTS
{
value_width = "16";
owner_width = "16";
value_init = "0";
owner_init = "0";
}
SIMULATION
{
DISPLAY
{
SIGNAL a
{
name = "address";
}
SIGNAL b
{
name = "chipselect";
}
SIGNAL c
{
name = "data_from_cpu";
radix = "hexadecimal";
}
SIGNAL d
{
name = "data_to_cpu";
radix = "hexadecimal";
}
SIGNAL e
{
name = "read";
}
SIGNAL f
{
name = "write";
}
SIGNAL g
{
name = "reset_reg";
radix = "hexadecimal";
}
SIGNAL h
{
name = "mutex_state";
radix = "hexadecimal";
}
SIGNAL i
{
name = "mutex_value";
radix = "hexadecimal";
}
SIGNAL j
{
name = "mutex_owner";
radix = "hexadecimal";
}
}
}
class = "altera_avalon_mutex";
class_version = "7.2";
SYSTEM_BUILDER_INFO
{
Is_Enabled = "1";
Clock_Source = "clk";
Has_Clock = "1";
}
}
}