www.pudn.com > Sparten3Epaomadeng.rar > hdpdeps.ref

V3 42 
FL D:/FPGA_Proj/paomadeng2/DCM_pao2.v 2008/04/25.14:34:12 J.30 
MO work/DCM_pao2 FL D:/FPGA_Proj/paomadeng2/DCM_pao2.v MI BUFG MI DCM_SP MI IBUFG 
FL D:/FPGA_Proj/paomadeng2/FreDiv10.v 2008/04/25.09:57:06 J.30 
MO work/FreDiv10 FL D:/FPGA_Proj/paomadeng2/FreDiv10.v 
FL D:/FPGA_Proj/paomadeng2/latch.v 2008/04/25.15:36:50 J.30 
MO work/latch FL D:/FPGA_Proj/paomadeng2/latch.v 
FL D:/FPGA_Proj/paomadeng2/MUX.v 2008/04/25.16:26:59 J.30 
MO work/MUX FL D:/FPGA_Proj/paomadeng2/MUX.v 
FL D:/FPGA_Proj/paomadeng2/paomadeng.v 2008/04/25.16:14:33 J.30 
MO work/paomadeng FL D:/FPGA_Proj/paomadeng2/paomadeng.v MI DCM_pao2 MI FreDiv10 \ 
      MI MUX MI latch MI patern1 MI patern2 
FL D:/FPGA_Proj/paomadeng2/patern1.v 2008/04/25.14:46:22 J.30 
MO work/patern1 FL D:/FPGA_Proj/paomadeng2/patern1.v 
FL D:/FPGA_Proj/paomadeng2/patern2.v 2008/04/25.14:50:07 J.30 
MO work/patern2 FL D:/FPGA_Proj/paomadeng2/patern2.v 
FL D:/FPGA_Proj/paomadeng2/testbench_latch.tfw 2008/04/25.15:24:43 J.30 
MO work/testbench_latch FL D:/FPGA_Proj/paomadeng2/testbench_latch.tfw MI latch 
FL D:/FPGA_Proj/paomadeng2/testbench_latch1.tfw 2008/04/25.15:36:49 J.30 
MO work/testbench_latch1 FL D:/FPGA_Proj/paomadeng2/testbench_latch1.tfw MI latch 
FL D:/FPGA_Proj/paomadeng2/testbench_mux.tfw 2008/04/25.15:05:33 J.30 
MO work/testbench_mux FL D:/FPGA_Proj/paomadeng2/testbench_mux.tfw MI MUX 
FL D:/FPGA_Proj/paomadeng2/testbench_mux2.tfw 2008/04/25.16:27:05 J.30 
MO work/testbench_mux2 FL D:/FPGA_Proj/paomadeng2/testbench_mux2.tfw MI MUX 
FL D:/FPGA_Proj/paomadeng2/testbench_paoma3.tfw 2008/04/25.16:38:34 J.30 
MO work/testbench_paoma3 FL D:/FPGA_Proj/paomadeng2/testbench_paoma3.tfw \ 
      MI paomadeng 
FL D:/FPGA_Proj/paomadeng2/testbench_paomadeng1.tfw 2008/04/25.16:21:59 J.30 
MO work/testbench_paomadeng1 FL D:/FPGA_Proj/paomadeng2/testbench_paomadeng1.tfw \ 
      MI paomadeng 
FL D:/FPGA_Proj/paomadeng2/testbench_patern1.tfw 2008/04/25.14:34:33 J.30 
MO work/testbench_patern1 FL D:/FPGA_Proj/paomadeng2/testbench_patern1.tfw \ 
      MI patern1 
FL D:/FPGA_Proj/paomadeng2/testbench_patern2.tfw 2008/04/25.14:48:45 J.30 
MO work/testbench_patern2 FL D:/FPGA_Proj/paomadeng2/testbench_patern2.tfw \ 
      MI patern2 
FL $XILINX/verilog/src/glbl.v 2006/12/02.07:44:50 J.30 
MO work/glbl FL $XILINX/verilog/src/glbl.v