www.pudn.com > Sparten3Epaomadeng.rar > hdllib.ref
MO testbench_paoma3 NULL D:/FPGA_Proj/paomadeng2/testbench_paoma3.tfw vlg44/testbench__paoma3.bin 1209112721 MO FreDiv10 NULL D:/FPGA_Proj/paomadeng2/FreDiv10.v vlg2D/_fre_div10.bin 1209110456 MO testbench_mux2 NULL D:/FPGA_Proj/paomadeng2/testbench_mux2.tfw vlg7B/testbench__mux2.bin 1209112028 MO testbench_paomadeng1 NULL D:/FPGA_Proj/paomadeng2/testbench_paomadeng1.tfw vlg68/testbench__paomadeng1.bin 1209111726 MO paomadeng NULL D:/FPGA_Proj/paomadeng2/paomadeng.v vlg04/paomadeng.bin 1209111282 MO testbench_latch1 NULL D:/FPGA_Proj/paomadeng2/testbench_latch1.tfw vlg08/testbench__latch1.bin 1209109018 MO testbench_patern1 NULL D:/FPGA_Proj/paomadeng2/testbench_patern1.tfw vlg22/testbench__patern1.bin 1209105287 MO testbench_patern2 NULL D:/FPGA_Proj/paomadeng2/testbench_patern2.tfw vlg23/testbench__patern2.bin 1209106217 MO MUX NULL D:/FPGA_Proj/paomadeng2/MUX.v vlg06/_m_u_x.bin 1209112027 MO latch NULL D:/FPGA_Proj/paomadeng2/latch.v vlg34/latch.bin 1209109017 MO DCM_pao2 NULL D:/FPGA_Proj/paomadeng2/DCM_pao2.v vlg35/_d_c_m__pao2.bin 1209110457 MO testbench_latch NULL D:/FPGA_Proj/paomadeng2/testbench_latch.tfw vlg2B/testbench__latch.bin 1209108332 MO testbench_mux NULL D:/FPGA_Proj/paomadeng2/testbench_mux.tfw vlg75/testbench__mux.bin 1209107142 MO glbl NULL D:/Xilinx91i/verilog/src/glbl.v vlg2D/glbl.bin 1209105288 MO patern1 NULL D:/FPGA_Proj/paomadeng2/patern1.v vlg03/patern1.bin 1209110455 MO patern2 NULL D:/FPGA_Proj/paomadeng2/patern2.v vlg04/patern2.bin 1209106216