www.pudn.com > Sparten3Epaomadeng.rar > FreDiv10.v

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    09:56:27 04/25/2008 
// Design Name: 
// Module Name:    FreDiv10 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module FreDiv10(clk, pclk);
    input clk;
    output pclk;
	  
	 reg pclk;
	 integer count;
			
	 initial
		count = 1;
			
	 always @(posedge clk)
		begin
			if(count > 10)
				count = 1;
			else
				count = count;
			

		
			if(count > 5)
				begin
					pclk = 1'b1;
					count = count+1;
				end
			else
				begin
					pclk = 1'b0;
					count = count+1;
				end
		end

endmodule