www.pudn.com > wavDEMO.zip > c5402_dsk.gel

/* set PMST to: MP =  OVLY = 1; DROM off, CLKOUT on */ 
#define PMST_VAL        0x00e0u   
 
/* set wait-state control reg for: 5  i/o; 1 ext memory */ 
#define SWWSR_VAL       0x5249u 
 
/* set external-banks switch control for: no bank switching; BH set */ 
#define BSCR_VAL        0x02u 
 
/* Set Default Reset Initialization Value */ 
#define    ZEROS        0x0000u 
 
/* Set CLKMD register to PLL multiplier of 5 */ 
#define    CLKMD_VAL    0x4007u 
 
 
 
/* Set Peripheral Control Register Addresses for DEV_RESET */ 
#define DMPREC          0x0054u 
#define DMSA            0x0055u 
#define DMSDI           0x0056u 
 
#define DMA_CH0_DMFSC_SUB_ADDR  0x0003u 
#define DMA_CH1_DMFSC_SUB_ADDR  0x0008u 
#define DMA_CH2_DMFSC_SUB_ADDR  0x000Du 
#define DMA_CH3_DMFSC_SUB_ADDR  0x0012u 
#define DMA_CH4_DMFSC_SUB_ADDR  0x0017u 
#define DMA_CH5_DMFSC_SUB_ADDR  0x001cu 
 
 
#define MCBSP0_SPSA     0x0038u 
#define MCBSP0_SPSD     0x0039u 
#define MCBSP1_SPSA     0x0048u 
#define MCBSP1_SPSD     0x0049u 
 
#define MCBSP2_SPSA     0x0034u 
#define MCBSP2_SPSD     0x0035u 
 
#define MCBSP_SPCR1_SUB_ADDR   0x0000u 
#define MCBSP_SPCR2_SUB_ADDR   0x0001u 
#define MCBSP_SRGR1_SUB_ADDR   0x0006u 
#define MCBSP_SRGR2_SUB_ADDR   0x0007u 
#define MCBSP_MCR1_SUB_ADDR    0x0008u 
#define MCBSP_MCR2_SUB_ADDR    0x0009u 
#define SRGR1_INIT             0x0001u 
 
#define PRD0            0x0025u 
#define TCR0            0x0026u 
 
#define PRD1            0x0031u 
#define TCR1            0x0032u 
#define CLKMD           0x0058u 
 
 
#define TIMER_STOP             0x0010u 
#define TIMER_RESET            0x0020u 
#define PRD_DEFAULT            0xFFFFu      
 
#define GPIOCR                 0x0010u 
  
 
 
 
/* The Startup() function is executed when the GEL file is loaded. */ 
 
StartUp() 
{ 
	C5402_DSK_Init();  
 
	GEL_TextOut("Gel StartUp Complete.\n"); 
} 
 
 
 
menuitem "C5402_DSK_Configuration"; 
hotmenu CPU_Reset() 
{ 
	GEL_Reset(); 
	PMST = PMST_VAL; 
 
	SWWSR = SWWSR_VAL; 
 
	BSCR = BSCR_VAL; 
 
	GEL_TextOut("CPU Reset Complete.\n"); 
} 
 
 
/* All memory maps are based on the PMST value of 0xFFE0 */ 
 
hotmenu C5402_DSK_Init() 
{ 
	GEL_Reset(); 
	PMST = PMST_VAL; 
 
	SWWSR = SWWSR_VAL; 
 
	BSCR = BSCR_VAL; 
 
	*(int *)CLKMD = CLKMD_VAL;  
 
	C5402_Periph_Reset(); 
 
	GEL_XMDef(0,0x1eu,1,0x8000u,0x7fu); 
	GEL_XMOn(); 
	GEL_MapOn(); 
	GEL_MapReset(); 
 
	GEL_MapAdd(0x80u,0,0x3F80u,1,1);	/* DARAM */ 
	GEL_MapAdd(0x4000u,0,0xC000u,1,1);	/* External */ 
	GEL_MapAdd(0x10000u,0,0xf0000u,1,1);	/* Extended Addressing - Page 0 */ 
 
	GEL_MapAdd(0x0u,1,0x60u,1,1);		/* MMRs */ 
	GEL_MapAdd(0x60u,1,0x3FA0u,1,1);	/* DARAM */ 
	GEL_MapAdd(0x4000u,1,0xC000u,1,1);	/* External */ 
 
	GEL_MapAdd(0x0u,2,0x10000u,1,1);	/* I/O space */ 
 
	*(int *)0x4@io = 0xff03u;		/* Enable SRAM */ 
 
	GEL_TextOut("C5402_DSK_Init Complete.\n"); 
} 
 
 
/* ****************************** */ 
 
C5402_Periph_Reset() 
{ 
	IFR = 0xFFFFu;   
	IFR = 0x0000u;   
 
	DMA_Reset(); 
	MCBSP0_Reset(); 
	MCBSP1_Reset(); 
	TIMER0_Reset(); 
	TIMER1_Reset(); 
	GPIO_Reset(); 
} 
 
 
DMA_Reset() 
{ 
	*(int *)DMPREC = ZEROS;   
     
	*(int *)DMSA = DMA_CH0_DMFSC_SUB_ADDR; 
	*(int *)DMSDI = ZEROS;      
	*(int *)DMSDI = ZEROS;      
	*(int *)DMSA  = DMA_CH1_DMFSC_SUB_ADDR; 
	*(int *)DMSDI = ZEROS;      
	*(int *)DMSDI = ZEROS;     
  
	*(int *)DMSA  = DMA_CH2_DMFSC_SUB_ADDR; 
	*(int *)DMSDI = ZEROS;      
	*(int *)DMSDI = ZEROS;      
  
	*(int *)DMSA  = DMA_CH3_DMFSC_SUB_ADDR; 
	*(int *)DMSDI = ZEROS;      
	*(int *)DMSDI = ZEROS;      
  
	*(int *)DMSA  = DMA_CH4_DMFSC_SUB_ADDR; 
	*(int *)DMSDI = ZEROS;      
	*(int *)DMSDI = ZEROS;     
  
	*(int *)DMSA  = DMA_CH2_DMFSC_SUB_ADDR; 
	*(int *)DMSDI = ZEROS;      
	*(int *)DMSDI = ZEROS;      
} 
 
MCBSP0_Reset() 
{ 
	*(int *)MCBSP0_SPSA = MCBSP_SPCR1_SUB_ADDR;     
	*(int *)MCBSP0_SPSD = ZEROS;                    
	*(int *)MCBSP0_SPSA = MCBSP_SPCR2_SUB_ADDR;     
	*(int *)MCBSP0_SPSD = ZEROS;  
                  
	*(int *)MCBSP0_SPSA = MCBSP_SRGR1_SUB_ADDR;     
	*(int *)MCBSP0_SPSD = SRGR1_INIT;               
	*(int *)MCBSP0_SPSA = MCBSP_SRGR2_SUB_ADDR;     
	*(int *)MCBSP0_SPSD = ZEROS;                    
 
	*(int *)MCBSP0_SPSA = MCBSP_MCR1_SUB_ADDR;      
	*(int *)MCBSP0_SPSD = ZEROS;                    
	*(int *)MCBSP0_SPSA = MCBSP_MCR2_SUB_ADDR;      
	*(int *)MCBSP0_SPSD = ZEROS;                    
} 
 
MCBSP1_Reset() 
{ 
	*(int *)MCBSP1_SPSA = MCBSP_SPCR1_SUB_ADDR;    
	*(int *)MCBSP1_SPSD = ZEROS;                    
	*(int *)MCBSP1_SPSA = MCBSP_SPCR2_SUB_ADDR;     
	*(int *)MCBSP1_SPSD = ZEROS;                    
 
	*(int *)MCBSP1_SPSA = MCBSP_SRGR1_SUB_ADDR;     
	*(int *)MCBSP1_SPSD = SRGR1_INIT;               
	*(int *)MCBSP1_SPSA = MCBSP_SRGR2_SUB_ADDR;     
	*(int *)MCBSP1_SPSD = ZEROS;    
                 
	*(int *)MCBSP1_SPSA = MCBSP_MCR1_SUB_ADDR;      
	*(int *)MCBSP1_SPSD = ZEROS;                    
	*(int *)MCBSP1_SPSA = MCBSP_MCR2_SUB_ADDR;      
	*(int *)MCBSP1_SPSD = ZEROS; 
}    
 
MCBSP2_Reset() 
{ 
	*(int *)MCBSP2_SPSA = MCBSP_SPCR1_SUB_ADDR;    
	*(int *)MCBSP2_SPSD = ZEROS;                    
	*(int *)MCBSP2_SPSA = MCBSP_SPCR2_SUB_ADDR;     
	*(int *)MCBSP2_SPSD = ZEROS; 
                    
	*(int *)MCBSP2_SPSA = MCBSP_SRGR1_SUB_ADDR;     
	*(int *)MCBSP2_SPSD = SRGR1_INIT;               
	*(int *)MCBSP2_SPSA = MCBSP_SRGR2_SUB_ADDR;     
	*(int *)MCBSP2_SPSD = ZEROS;    
                 
	*(int *)MCBSP2_SPSA = MCBSP_MCR1_SUB_ADDR;      
	*(int *)MCBSP2_SPSD = ZEROS;                    
	*(int *)MCBSP2_SPSA = MCBSP_MCR2_SUB_ADDR;      
	*(int *)MCBSP2_SPSD = ZEROS; 
}    
 
TIMER0_Reset() 
{ 
	*(int *)TCR0 = TIMER_STOP;               
	*(int *)PRD0 = PRD_DEFAULT;               
	*(int *)TCR0 = TIMER_RESET; 
} 
 
TIMER1_Reset() 
{      
 
	*(int *)TCR1 = TIMER_STOP;                
	*(int *)PRD1 = PRD_DEFAULT;               
	*(int *)TCR1 = TIMER_RESET;               
}   
 
GPIO_Reset() 
{ 
	*(int *)GPIOCR = ZEROS; 
}