[file head]:
!PADS-POWERPCB-V2005.0-MILS! DESIGN DATABASE ASCII FILE 1.0
*PCB* GENERAL PARAMETERS OF THE PCB DESIGN

UNITS 0 2=Inches 1=Metric 0=Mils
USERGRID 5 5 Space between USER grid points
MAXIMUMLAYER 10 Maximum routing layer
WORKLEVEL 30 Level items will be created on
DISPLAYLEVEL 1 toggle for displaying working level last
LAYERPAIR 1 10 Layer pair used to route connection
VIAMODE T Type of via to use when routing between layers
LINEWIDTH 10 Width items will be created with
TEXTSIZE 70 8 Height and LineWidth text will be created with
JOBTIME 39422 Amount of time spent on this PCB design
DOTGRID 50 50 Space between graphic dots
SCALE 14.743 Scale of window expansion
ORIGIN 28250 28250 User defined origin location
WINDOWCENTER 40159.32 25328.93 Point defining the center of the window
... ...

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... ...
Vias" No
"DFT.Preserve Test Points" No
"DFT.Probe Pins" Yes
"DFT.Probe to Pad Clearance" 6.00mil
"DFT.Probe to Trace Clearance" 6.00mil
"DFT.Stub Length" 150.00mil
"DFT.Use Via Grid" Yes
Placement.Grid.Use No
Placement.Grid.X 5.00mil
Placement.Grid.Y 5.00mil
Routing.MaxChannelWidth 100.00mil
Routing.MeanderBeforeTune No
Routing.SoftLengthRrules Yes
Rules.ViaAtSMD No
Rules.Fanout.Alignment Alternate
Rules.Fanout.Direction Both Sides
Rules.Fanout.ViaSpacing Use Grid
Rules.Fanout.Alignment.Multi-Row Yes
Rules.Fanout.Length.Unlimited Yes
Rules.Fanout.Nets.Plane Yes
Rules.Fanout.Nets.Signal No
Rules.Fanout.Nets.UnusedPins No
Rules.Fanout.Sharing.Pin Yes
Rules.Fanout.Sharing.SMD Yes
Rules.Fanout.Sharing.Trace Yes
Rules.Fanout.Sharing.Via Yes
Rules.PadEntry.AnyAngle Yes
Rules.PadEntry.Corner Yes
Rules.PadEntry.Side Yes
Rules.PadEntry.Soft Yes
Rules.ViaAtSMD.Center Yes
Rules.ViaAtSMD.Ends Yes
Rules.ViaAtSMD.FitInside Yes
}
}

*END* OF ASCII OUTPUT FILE