www.pudn.com > fifov1.rar > fifotestbench.v

// -------------------------------------------------------------------- 
// >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< 
// -------------------------------------------------------------------- 
// Copyright (c) 2005 by DTK Corporation 
// -------------------------------------------------------------------- 
// -------------------------------------------------------------------- 
// 
// This is the testbench file for the fast FIFO  
//controller reference design. 
// 
// -------------------------------------------------------------------- 
// 
// Revision History :  
// -------------------------------------------------------------------- 
//   Ver  :| Author            :| Mod. Date :| Changes Made: 
//   V0.1 :| Robin Liu         :| 03/29/05  :| Pre-Release 
// -------------------------------------------------------------------- 
`timescale 1ns / 100ps 
 
module fifotestbench(empty,full,dout); 
`include "FIFOPar.v" 
output empty,full; 
output [`FIFODataWidth-1:0] dout; 
reg rst,wren,wr_clk,rden,rd_clk; 
reg[`FIFODataWidth-1:0] din; 
 
initial  
begin  
rst=0; 
#42 rst=1; 
end 
 
initial  
begin  
wren=0; 
#225 wren=1; 
#(83600) wren=0; 
#100000 wren=1; 
#100 wren=0; 
end  
 
initial  
begin  
 rden=0; 
 #(83705) rden=1; 
 #100000 rden=0; 
 #180    rden=1; 
 #100    rden=0; 
 #100    rden=1; 
# 200    rden=0; 
end  
 
initial  
begin  
wr_clk=0; 
forever #10 wr_clk=!wr_clk; 
end 
 
initial  
begin  
 din=0; 
#5 forever #20 din=din+1;  
end 
 
 
initial  
begin  
rd_clk=0; 
forever #10 rd_clk=!rd_clk; 
end 
 
 
fifoTop toplevel(.empty(empty),.full(full),.dout(dout), 
                 .rst(rst),.wr_clk(wr_clk),.wren(wren),.din(din), 
                 .rd_clk(rd_clk),.rden(rden)); 
 
endmodule