www.pudn.com > fifov1.rar > emptyFullGen.v

// -------------------------------------------------------------------- 
// >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< 
// -------------------------------------------------------------------- 
// Copyright (c) 2005 by DTK Corporation 
// -------------------------------------------------------------------- 
// -------------------------------------------------------------------- 
// 
// This file is the empty and full signal-generator of the fast FIFO  
//controller reference design. 
// 
// -------------------------------------------------------------------- 
// 
// Revision History :  
// -------------------------------------------------------------------- 
//   Ver  :| Author            :| Mod. Date :| Changes Made: 
//   V0.1 :| Robin Liu         :| 03/29/05  :| Pre-Release 
// -------------------------------------------------------------------- 
`timescale 1ns / 100ps 
 
module emptyFullGen(full,empty,rst,wr_clk,dpwraddress,wr_page, 
                    rd_clk,rden,dprdaddress,rd_page); 
`include "FIFOPar.v" 
output empty,full; 
input rst,wr_clk,rd_clk,wr_page,rd_page,rden; 
input[`FIFOAddrDepth-1 : 0] dpwraddress,dprdaddress; 
reg empty,full; 
wire [`FIFOAddrDepth-1 : 0] dpra,dpraGray; 
wire[`FIFOAddrDepth-1 : 0] dpwraddressGray,dprdaddressGray; 
 
assign dpra=(rden & (!empty))?  ((dprdaddress==0) ? `FIFOMaxAddressValue : (dprdaddress-1))  
                                    : dprdaddress; 
assign dpwraddressGray=dpwraddress ^ {1'b0,dpwraddress[`FIFOAddrDepth-1:1]}; 
assign dprdaddressGray=dprdaddress ^ {1'b0,dprdaddress[`FIFOAddrDepth-1:1]}; 
assign dpraGray=dpra ^ {1'b0,dpra[`FIFOAddrDepth-1:1]}; 
assign dpra=(rden & (!empty))?  ((dprdaddress==0) ? `FIFOMaxAddressValue : (dprdaddress-1))  
                                    : dprdaddress; 
always@( rst or dpwraddressGray or dprdaddressGray or wr_page or rd_page) 
   if (!rst) 
      #tDLY full=0; 
   else #tDLY 
     if ((dpwraddressGray==dpraGray) & (wr_page ^ rd_page)) 
            full=1; 
     else 
           full=0;  
 
always@(posedge rd_clk or negedge rst) 
   if (!rst) 
       #tDLY empty=1; 
   else  
      case(rden) 
       1 : if (dprdaddressGray==dpwraddressGray) 
                  #tDLY  empty=1; 
       default : begin if ((dprdaddressGray==dpwraddressGray) & (wr_page ~^ rd_page)) 
                         #tDLY empty=1; 
                       else 
                         #tDLY empty=0; 
                 end 
      endcase 
endmodule