[file head]:
// Copyright (C) 1988-2004 Altera Corporation
// Any megafunction design, and related netlist (encrypted or decrypted),
// support information, device programming or simulation file, and any other
// associated documentation or information provided by Altera or a partner
// under Altera's Megafunction Partnership Program may be used only
// to program PLD devices (but not masked PLD devices) from Altera. Any
// other use of such megafunction design, netlist, support information,
// device programming or simulation file, or any other related documentation
// or information is prohibited for any other purpose, including, but not
// limited to modification, reverse engineering, de-compiling, or use with
// any other silicon devices, unless such use is explicitly licensed under
// a separate agreement with Altera or a megafunction partner. Title to the
// intellectual property, including patents, copyrights, trademarks,
... ...

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... ...
d_trans[18:16] <= masterhsize_out;
end
else if ( ( ~address_bus_owned &amt; masterhready_in) | reset)
d_trans<= i_trans;


always @(posedge masterhclk_in)
if (trans_end &amt; ~need_retry)
begin
r_trans[253:252]<=masterhresp_in;
r_trans[251:220]<=masterhrdata_in;
r_trans[219:0] <=d_trans[219:0];
end
else if (trans_end &amt; need_retry)
begin
r_trans[253:252]<=masterhresp_in;
r_trans[251:220]<=masterhrdata_in;
r_trans[219:0] <=retry_trans[219:0];
end
else
r_trans<=i_trans;


/*----------------------------------------------------------------------------
masterhlock_out
----------------------------------------------------------------------------*/
assign masterhlock_out = 1'b0;
/*----------------------------------------------------------------------------
----------------------------------------------------------------------------*/
endmodule // alt_exc_upcore