www.pudn.com > fifov1.rar > FIFOdpRAMInterface.v

// -------------------------------------------------------------------- 
// >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< 
// -------------------------------------------------------------------- 
// Copyright (c) 2005 by DTK Corporation 
// -------------------------------------------------------------------- 
// -------------------------------------------------------------------- 
// 
// This file contains the all interfaces with dual port RAM in the fast 
// FIFO controller reference design. 
// 
// -------------------------------------------------------------------- 
// 
// Revision History :  
// -------------------------------------------------------------------- 
//   Ver  :| Author            :| Mod. Date :| Changes Made: 
//   V0.1 :| Robin Liu         :| 03/29/05  :| Pre-Release 
// -------------------------------------------------------------------- 
`timescale 1ns / 100ps 
module FIFOdpRAMInterface(full,empty,dpwren,dpdin,dpwraddress,dprdaddress,dout, 
                          rst,wren,wr_clk,din,rden,rd_clk,dpdout); 
`include "FIFOPar.v" 
output full,empty,dpwren; 
output [`FIFODataWidth-1:0] dpdin,dout; 
output [`FIFOAddrDepth-1:0] dpwraddress,dprdaddress;  
input rst,wren,wr_clk,rden,rd_clk; 
input [`FIFODataWidth-1:0] din,dpdout; 
 
wire wr_page,rd_page; 
 
FIFOWriteGen writegen(.wr_page(wr_page),.dpwraddress(dpwraddress),.dpwren(dpwren),.dpdin(dpdin), 
             .rst(rst),.wren(wren),.wr_clk(wr_clk),.full(full),.din(din)); 
FIFOReadGen readgen(.rd_page(rd_page),.dprdaddress(dprdaddress),.dout(dout), 
            .rst(rst),.rd_clk(rd_clk),.rden(rden),.empty(empty),.dpdout(dpdout)); 
emptyFullGen emptyfullgen(.full(full),.empty(empty),.rst(rst),.wr_clk(wr_clk),.dpwraddress(dpwraddress), 
             .wr_page(wr_page),.rd_clk(rd_clk),.rden(rden),.dprdaddress(dprdaddress),.rd_page(rd_page)); 
 
endmodule