www.pudn.com > fifov1.rar > FIFOWriteGen.v

// -------------------------------------------------------------------- 
// >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< 
// -------------------------------------------------------------------- 
// Copyright (c) 2005 by DTK Corporation 
// -------------------------------------------------------------------- 
// -------------------------------------------------------------------- 
// 
// This file is the write-generator of the fast FIFO  
//controller reference design. 
// 
// -------------------------------------------------------------------- 
// 
// Revision History :  
// -------------------------------------------------------------------- 
//   Ver  :| Author            :| Mod. Date :| Changes Made: 
//   V0.1 :| Robin Liu         :| 03/29/05  :| Pre-Release 
// -------------------------------------------------------------------- 
`timescale 1ns / 100ps 
module FIFOWriteGen(wr_page,dpwraddress,dpwren,dpdin,rst,wren,wr_clk,full,din); 
`include "FIFOPar.v" 
output[`FIFOAddrDepth-1:0] dpwraddress; 
output[`FIFODataWidth-1:0] dpdin; 
output wr_page,dpwren; 
input [`FIFODataWidth-1:0] din; 
input rst,wren,wr_clk,full; 
 
reg[`FIFOAddrDepth-1:0] dpwraddress; 
reg[`FIFODataWidth-1:0] dpdin; 
reg wr_page; 
wire dpwren; 
wire [`FIFODataWidth-1:0] dpdreg;  
 
assign dpwren=(!full) & wren; 
assign dpdreg=din; 
always@(dpdreg) 
  dpdin=dpdreg;   
 
 
//writing  
always@(posedge wr_clk or negedge rst) 
    if (!rst) #tDLY 
       begin  
       dpwraddress=0; 
       wr_page=0; 
       end 
    else if ((wren) & (!full)) 
         case (dpwraddress) 
           `FIFOMaxAddressValue: #tDLY begin  dpwraddress=0; wr_page=!wr_page; end 
            default:     #tDLY   dpwraddress=dpwraddress+1;  
         endcase 
 
endmodule