www.pudn.com > fifov1.rar > FIFOReadGen.v

// -------------------------------------------------------------------- 
// >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< 
// -------------------------------------------------------------------- 
// Copyright (c) 2005 by DTK Corporation 
// -------------------------------------------------------------------- 
// -------------------------------------------------------------------- 
// 
// This file is the read-generator of the fast FIFO  
//controller reference design. 
// 
// -------------------------------------------------------------------- 
// 
// Revision History :  
// -------------------------------------------------------------------- 
//   Ver  :| Author            :| Mod. Date :| Changes Made: 
//   V0.1 :| Robin Liu         :| 03/29/05  :| Pre-Release 
// -------------------------------------------------------------------- 
`timescale 1ns / 100ps     
module FIFOReadGen(rd_page,dprdaddress,dout,rst,rd_clk,rden,empty,dpdout); 
`include "FIFOPar.v" 
output[`FIFOAddrDepth-1:0] dprdaddress ; 
output[`FIFODataWidth-1:0] dout; 
output rd_page; 
input [`FIFODataWidth-1:0] dpdout; 
input rst,rd_clk,rden,empty; 
reg rd_page; 
reg [`FIFOAddrDepth-1:0] dprdaddressTemp; 
wire [`FIFODataWidth-1:0] dout; 
 
// when rden=1, FIFO out is enable 
assign #tDLY dout=rden? dpdout :`FIFODataWidth'bz; 
 
always@(posedge rd_clk or negedge rst)  
  if (!rst) #tDLY begin  
     dprdaddressTemp=0; 
     rd_page=0; end 
  else if (rden & (!empty)) 
      case(dprdaddressTemp) 
           `FIFOMaxAddressValue:#tDLY  begin  dprdaddressTemp=0; rd_page=!rd_page; end 
            default             : #tDLY dprdaddressTemp=dprdaddressTemp+1; 
      endcase     
assign dprdaddress=(rden & (!empty))?  ((dprdaddressTemp==`FIFOMaxAddressValue) ? `FIFOAddrDepth'b0 : (dprdaddressTemp+1))  
                                    : dprdaddressTemp; 
       
endmodule