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// -------------------------------------------------------------------- 
// >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< 
// -------------------------------------------------------------------- 
// Copyright (c) 2005 by DTK Corporation 
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// -------------------------------------------------------------------- 
// 
// This file contains the parameters used in the fast FIFO controller 
// reference design. 
// 
// -------------------------------------------------------------------- 
// 
// Revision History :  
// -------------------------------------------------------------------- 
//   Ver  :| Author            :| Mod. Date :| Changes Made: 
//   V0.1 :| Robin Liu         :| 03/29/05  :| Pre-Release 
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parameter tDLY = 2; // 2ns delay for simulation purpose 
 
//data width of the dual port RAM  
`ifdef FIFODataWidth          //data width =16; 
`undef FIFODataWidth 
`endif 
`define FIFODataWidth  16  
 
//the dual port RAM capacitibility 
`ifdef FIFOCap                // capacity: 64*1024=65536bits; 
`undef FIFOCap 
`endif 
`define FIFOCap 64*1024 
 
// maxium address value of the dual port RAM 
`ifdef FIFOMaxAddressValue 
`undef FIFOMaxAddressValue 
`endif 
`define FIFOMaxAddressValue (`FIFOCap/`FIFODataWidth)-1 
 
//address depth of the dual port RAM 
`ifdef FIFOAddrDepth          // address depth=12 ; 
`undef FIFOAddrDepth 
`endif 
`define FIFOAddrDepth 12