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//-------------------------------------------------------------------------
// This Verilog file was developed by Altera Corporation. It may be
// freely copied and/or distributed at no cost. Any persons using this
// file for any purpose do so at their own risk, and are responsible for
// the results of such use. Altera Corporation does not guarantee that
// this file is complete, correct, or fit for any particular purpose.
// NO WARRANTY OF ANY KIND IS EXPRESSED OR IMPLIED. This notice must
// accompany any copy of this file.
//------------------------------------------------------------------------
//
// Quartus II 4.0 Build 214 1/28/2004
//
//------------------------------------------------------------------------
// LPM Synthesizable Models (Support string type generic)
// These models are based on LPM version 220 (EIA-IS103 October 1998).
//------------------------------------------------------------------------
//
//------------------------------------------
... ...

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er lpm_hint = "UNUSED";

// INPUT PORT DECLARATION
input [lpm_width-1:0] data;
input enable;

// OUTPUT PORT DECLARATION
output [lpm_width-1:0] result;

// INPUT/OUTPUT PORT DECLARATION
inout [lpm_width-1:0] pad;

// INTERNAL REGISTER/SIGNAL DECLARATION
reg [lpm_width-1:0] tmp_pad;
reg [lpm_width-1:0] result;

// INITIAL CONSTRUCT BLOCK
initial
begin
if (lpm_width <= 0)
begin
$display("Value of lpm_width parameter must be greater than 0(ERROR)");
$finish;
end
end

// ALWAYS CONSTRUCT BLOCK
always @(data or pad or enable)
begin
if (enable == 1)
begin
tmp_pad = data;
result = 'bz;
end
else if (enable == 0)
begin
result = pad;
tmp_pad = 'bz;
end
end

// CONTINOUS ASSIGNMENT
assign pad = tmp_pad;

endmodule // lpm_bipad
// END OF MODULE