www.pudn.com > at91rm9200vxworksbsp.rar > romInit.s
/*
* armboot - Startup Code for AT91RM9200 CPU-core
*
* Copyright (c) 2001 Marius Gröger
* Copyright (c) 2002 Alex Züpke
* Copyright (c) 2002 Gary Jennejohn
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#define _ASMLANGUAGE
#include "vxWorks.h"
#include "sysLib.h"
#include "asm.h"
#include "regs.h"
#include "config.h"
#include "arch/arm/mmuArmLib.h"
#include "at91rm9200dk.h"
/* flash */
#define MC_PUIA 0xFFFFFF10
#define MC_PUP 0xFFFFFF50
#define MC_PUER 0xFFFFFF54
#define MC_ASR 0xFFFFFF04
#define MC_AASR 0xFFFFFF08
#define EBI_CFGR 0xFFFFFF64
#define SMC2_CSR 0xFFFFFF70
/* PMC */
#define PMC_SCER 0xFFFFFC00
#define PMC_SCDR 0xFFFFFC04
#define PMC_PCER 0xFFFFFC10
#define PMC_PCDR 0xFFFFFC14
#define CKGR_MOR 0xFFFFFC20
#define CKGR_PLLAR 0xFFFFFC28
#define CKGR_PLLBR 0xFFFFFC2C
#define PMC_MCKR 0xFFFFFC30
#define PMC_PCK0 0xFFFFFC40
#define PMC_PCK1 0xFFFFFC44
#define PMC_PCK2 0xFFFFFC48
#define PMC_PCK3 0xFFFFFC4C
#define PMC_IER 0xFFFFFC60
#define PMC_IDR 0xFFFFFC64
#define ICCR 0xFFFFF128
#define IDCR 0xFFFFF124
/* sdram */
#define PIOC_ASR 0xFFFFF870
#define PIOC_BSR 0xFFFFF874
#define PIOC_PDR 0xFFFFF804
#define EBI_CSA 0xFFFFFF60
#define SMC_CSR0 0xFFFFFF70
#define SDRC_CR 0xFFFFFF98
#define SDRC_MR 0xFFFFFF90
#define SDRC_TR 0xFFFFFF94
#define SVC_STACK_SIZE 0x10
#define IRQ_STACK_SIZE 0x10
#define FIQ_STACK_SIZE 0x04
#define ABT_STACK_SIZE 0x04
#define UND_STACK_SIZE 0x04
#define USER_STACK_SIZE 0x400
/*
* Count for a CPU delay loop at the beginning of romInit. There have been
* reports of problems with certain boards and certain power supplies, and
* adding a delay at the start of romInit appears to help with this. This
* value may need tuning for different board/PSU combinations.
*/
#define AT91_DELAY_VALUE 0x1000
.data
.globl VAR(copyright_wind_river)
.long VAR(copyright_wind_river)
#define TEXT_BASE ROM_TEXT_ADRS
/* internals */
.globl FUNC(romInit) /* start of system code */
.globl VAR(sdata) /* start of data */
.globl _sdata
.globl VAR(integratorMemSize) /* actual memory size */
/* externals */
.extern FUNC(romStart)
.extern FUNC(AT91F_LowLevelInit)
.extern FUNC(system_sdram_check)
_sdata:
VAR_LABEL(sdata)
.asciz "start of data"
.balign 4
/* variables */
.data
VAR_LABEL(integratorMemSize)
.long 0
.text
.balign 4
/*
*************************************************************************
*
* Jump vector table as in table 3.1 in [1]
*
*************************************************************************
*/
.globl _start
_ARM_FUNCTION(romInit)
_romInit:
_start:
b reset
B .
B .
B .
B .
B .
B .
B .
.ascii "Grentech\n."
.balign 4
/*
*************************************************************************
*
* Startup Code (reset vector)
*
* do important init only if we don't start from memory!
* relocate armboot to ram
* setup stack
* jump to second stage
*
*************************************************************************
*/
reset:
ldr r1, =CKGR_MOR
#ifdef CFG_USE_MAIN_OSCILLATOR
ldr r0, =0x0000FF01 /* Enable main oscillator, OSCOUNT = 0xFF */
#else
ldr r0, =0x0000FF00 /* Disable main oscillator, OSCOUNT = 0xFF */
#endif
str r0, [r1]
/*Add loop to compensate Main Oscillator startup time*/
ldr r0, =0x00000010
LoopOsc:
subs r0, r0, #1
bhi LoopOsc
/*Set up Supervisor Mode and set SVC Stack*/
ldr r1, = 0x00204000
/*Setting:
(1) disable IRQ and FIQ interrupts
(2) code run in ARM state
(3) processor run in SVC
*/
mrs r0,cpsr
bic r0,r0,#0x1f
orr r0,r0,#0xd3
msr cpsr,r0
/*Insure word alignement*/
bic r1, r1, #3
/*Init stack SYS*/
mov sp, r1
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
/*****************************
*****************************
Initialize ARM core
*****************************
*****************************/
/* flush(invalidate) v4 I/D caches */
mov r0, #0
mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
/*
* disable MMU stuff and caches
*/
mrc p15, 0, r0, c1, c0, 0
/*
(1) choose the location of exception table : 0x00000000~0x0000001c;
(2) system and rom protection
*/
bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
/*
(1) choose little-endian
(2) disable D-Cache
(3) disable MMU
*/
bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
/*
(1) enable adderee align check
*/
orr r0, r0, #0x00000002 @ set bit 2 (A) Align
/*
(1) enable I-Cache
*/
orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
mcr p15, 0, r0, c1, c0, 0
#ifndef BOOTROM_START_FROM_RAM
bl AT91F_LowLevelInit
bl system_sdram_check
#endif
#endif
/** Initialize the stack pointer to just before where the
* uncompress code, copied from ROM to RAM, will run. */
ldr sp, __boot_stack
mov fp, #0 /* zero frame pointer */
/* jump to C entry point in ROM: routine - entry point + ROM base */
MOV r0, #BOOT_COLD
ldr pc, _start_armboot
/*
* PC-relative-addressable pointers - LDR Rn,=sym is broken
* note "_" after "$" to stop preprocessor performing substitution
*/
.balign 4
_start_armboot:
.long ROM_TEXT_ADRS + FUNC(romStart) - FUNC(romInit)
__boot_stack:
.word STACK_ADRS