www.pudn.com > at91rm9200vxworksbsp.rar > at91rm9200dk.h
/*
* linux/include/asm-arm/arch-at91rm9200/at91rm9200dk.h
*
* Copyright (c) 2003 SAN People
* Copyright (c) 2003 ATMEL
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
*/
#ifndef __AT91RM9200DK_H
#define __AT91RM9200DK_H
/* System BUS Type */
#define BUS BUS_TYPE_NONE
/****************************************************************************************
AT91's Peripheral Configuration
*******************************************************************************************/
/*********************************** PMC *********************************************/
#define MASTER_CLOCK 60000000
/* AT91RM92000 clocks */
#define AT91C_MAIN_CLOCK 179712000 /* from 18.432 MHz crystal (18432000 / 4 * 39) */
#define AT91C_MASTER_CLOCK 59904000 /* peripheral clock */
#define AT91C_SLOW_CLOCK 32768 /* slow clock */
#define AT91_PLLB_INIT 0x1048be0e /* (18.432 / 14 * 73) /2 = 47.9714 */
#define CPLL_FREQ 180 /* 166 Mhz */
#define SYS_TIMER_CLK (AT91C_MAIN_CLOCK/16)
#define AUX_TIMER_CLK SYS_TIMER_CLK
/*********************************** SDRAMC *********************************************/
#define AT91_SDRAM_BASE 0x20000000
/*********************************** DBGU *********************************************/
#define INCLUDE_SERIAL
#ifdef INCLUDE_SERIAL
#define AT91C_CONSOLE_DEFAULT_BAUDRATE CONSOLE_BAUD_RATE /* default serial console baud-rate */
#define N_SIO_CHANNELS 1 /* No. serial I/O channels */
#define AT91C_DBGU_PDC_MODE
#endif
/*********************************** ST *********************************************/
#define INCLUDE_ST_RTT /* Real Time Timer of System Timer Configuration:
define to create time interrupt every 1 second */
/*********************************** TC *********************************************/
#define INCLUDE_TIMER_COUNTERS
#ifdef INCLUDE_TIMER_COUNTERS
/* Limits
MIN : CLK = AT91C_TC_TIMER_DIV1_CLOCK; RC = (AT91C_MASTER_CLOCK/2)/50000; 20us
MAX : CLK = AT91C_TC_TIMER_DIV4_CLOCK; RC = 0xFFFF; 140ms
*/
#define TIMER_COUNTER_RATE_MIN 10 /* minimum auxiliary clock rate */
#define TIMER_COUNTER_RATE_MAX 500000 /* maximum auxiliary clock rate */
#endif /* INCLUDE_TIMER_COUNTERS */
/*********************************** AIC *********************************************/
/*
* Interrupt mode - interrupts can be in either preemptive or non-preemptive
* mode. For non-preemptive mode, change INT_MODE to INT_NON_PREEMPT_MODEL
*/
#define INT_MODE INT_PREEMPT_MODEL
/* Peripheral interrupt configuration */
#define AT91_SMR_FIQ (AT91C_AIC_PRIOR_HIGHEST | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE) /* Advanced Interrupt Controller (FIQ)*/
#define AT91_SMR_SYS (AT91C_AIC_PRIOR_6 | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE) /* System Peripheral*/
#define AT91_SMR_PIOA (AT91C_AIC_PRIOR_LOWEST | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE) /* Parallel IO Controller A*/
#define AT91_SMR_PIOB (AT91C_AIC_PRIOR_LOWEST | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE) /* Parallel IO Controller B*/
#define AT91_SMR_PIOC (AT91C_AIC_PRIOR_LOWEST | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE) /* Parallel IO Controller C*/
#define AT91_SMR_PIOD (AT91C_AIC_PRIOR_LOWEST | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE) /* Parallel IO Controller D*/
#define AT91_SMR_US0 (AT91C_AIC_PRIOR_5 | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE) /* USART 0*/
#define AT91_SMR_US1 (AT91C_AIC_PRIOR_5 | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE) /* USART 1*/
#define AT91_SMR_US2 (AT91C_AIC_PRIOR_5 | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE) /* USART 2*/
#define AT91_SMR_US3 (AT91C_AIC_PRIOR_5 | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE) /* USART 3*/
#define AT91_SMR_MCI (AT91C_AIC_PRIOR_LOWEST | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE) /* Multimedia Card Interface*/
#define AT91_SMR_UDP (AT91C_AIC_PRIOR_3 | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE) /* USB Device Port*/
#define AT91_SMR_TWI (AT91C_AIC_PRIOR_LOWEST | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE) /* Two-Wire Interface*/
#define AT91_SMR_SPI (AT91C_AIC_PRIOR_6 | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE) /* Serial Peripheral Interface*/
#define AT91_SMR_SSC0 (AT91C_AIC_PRIOR_4 | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE) /* Serial Synchronous Controller 0*/
#define AT91_SMR_SSC1 (AT91C_AIC_PRIOR_4 | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE) /* Serial Synchronous Controller 1*/
#define AT91_SMR_SSC2 (AT91C_AIC_PRIOR_4 | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE) /* Serial Synchronous Controller 2*/
#define AT91_SMR_TC0 (AT91C_AIC_PRIOR_LOWEST | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE) /* Timer Counter 0*/
#define AT91_SMR_TC1 (AT91C_AIC_PRIOR_LOWEST | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE) /* Timer Counter 1*/
#define AT91_SMR_TC2 (AT91C_AIC_PRIOR_LOWEST | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE) /* Timer Counter 2*/
#define AT91_SMR_TC3 (AT91C_AIC_PRIOR_LOWEST | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE) /* Timer Counter 3*/
#define AT91_SMR_TC4 (AT91C_AIC_PRIOR_LOWEST | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE) /* Timer Counter 4*/
#define AT91_SMR_TC5 (AT91C_AIC_PRIOR_LOWEST | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE) /* Timer Counter 5*/
#define AT91_SMR_UHP (AT91C_AIC_PRIOR_2 | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE) /* USB Host port*/
#define AT91_SMR_EMAC (AT91C_AIC_PRIOR_2 | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE) /* Ethernet MAC*/
#define AT91_SMR_IRQ0 (AT91C_AIC_PRIOR_HIGHEST | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE) /* Advanced Interrupt Controller (IRQ0)*/
#define AT91_SMR_IRQ1 (AT91C_AIC_PRIOR_LOWEST | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE) /* Advanced Interrupt Controller (IRQ1)*/
#define AT91_SMR_IRQ2 (AT91C_AIC_PRIOR_LOWEST | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE) /* Advanced Interrupt Controller (IRQ2)*/
#define AT91_SMR_IRQ3 (AT91C_AIC_PRIOR_LOWEST | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE) /* Advanced Interrupt Controller (IRQ3)*/
#define AT91_SMR_IRQ4 (AT91C_AIC_PRIOR_LOWEST | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE) /* Advanced Interrupt Controller (IRQ4)*/
#define AT91_SMR_IRQ5 (AT91C_AIC_PRIOR_LOWEST | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE) /* Advanced Interrupt Controller (IRQ5)*/
#define AT91_SMR_IRQ6 (AT91C_AIC_PRIOR_LOWEST | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE) /* Advanced Interrupt Controller (IRQ6)*/
/*********************************** EMAC *********************************************/
/* Memory Map for Buffer Descriptor and Buffer */
#define ETH_MAX_UNITS 1
#if (USER_RESERVED_MEM > 0)
#define USER_BASE_ADRS (LOCAL_MEM_LOCAL_ADRS + LOCAL_MEM_SIZE - USER_RESERVED_MEM)
#define USER_SIZE (USER_RESERVED_MEM)
#else /* (USER_RESERVED_MEM > 0) */
#endif /* (USER_RESERVED_MEM > 0) */
/*********************************** NAND FLASH *********************************************/
#define INCLUDE_NAND_FLASH /** NAND flash configuration **/
#ifdef INCLUDE_NAND_FLASH
#define AT91_NANDFLASH_BASE 0x40000000 /* NCS3: Smartmedia physical base address*/
#define NAND_BOOT_PARAMETERS_ADRS 0x000800000
#define NAND_MAC_ADRS 0x000900000
#define NAND_FLASH_1ST_HALF_PAGE_BYTES 256
#define NAND_FLASH_2ND_HALF_PAGE_BYTES 256
#define NAND_FLASH_MAIN_BYTES_PER_PAGE (NAND_FLASH_1ST_HALF_PAGE_BYTES + NAND_FLASH_2ND_HALF_PAGE_BYTES)
#define NAND_FLASH_SPARE_BYTES_PER_PAGE 16
#define NAND_FLASH_BYTES_PER_PAGE (NAND_FLASH_MAIN_BYTES_PER_PAGE + NAND_FLASH_SPARE_BYTES_PER_PAGE)
#define NAND_FLASH_PAGES_PER_BLOCK 32
#define NAND_FLASH_BLOCK_PER_CHIP 2048
#define NAND_FLASH_PAGE_SIZE NAND_FLASH_BYTES_PER_PAGE
#define NAND_FLASH_BLOCK_SIZE (NAND_FLASH_PAGES_PER_BLOCK * NAND_FLASH_PAGE_SIZE)
#define NAND_FLASH_SIZE (NAND_FLASH_BLOCK_PER_CHIP * NAND_FLASH_BLOCK_SIZE)
#define NAND_FLASH_ROWS (NAND_FLASH_BLOCK_PER_CHIP * NAND_FLASH_PAGES_PER_BLOCK)
#define NAND_FLASH_COLUMNS NAND_FLASH_BYTES_PER_PAGE
#endif /* INCLUDE_NAND_FLASH */
/*********************************** NOR FLASH *********************************************/
#define AT91_FLASH_BASE 0x10000000 /* NCS0: Nor Flash physical base address*/
#define AT91_FLASH_SIZE 0x2000000 /* 32M bytes */
#undef INCLUDE_NOR_FLASH /** NOR flash configuration **/
#ifdef INCLUDE_NOR_FLASH
#undef AT91_NOR_FLASH_16M_TO_32M
#ifdef AT91_NOR_FLASH_16M_TO_32M
#define NOR_FLASH_TFFS_SIZE_IN_BYTES 0x1f00000 /*15M bytes --> 31M bytes wurj 1110*/
#else
#define NOR_FLASH_TFFS_SIZE_IN_BYTES 0xf00000 /*15M bytes*/
#endif
#define NOR_FLASH_TFFS_OFFSET 0x100000 /*leave 1M bytes for bootrom*/
#define NOR_FLASH_SECTOR_SIZE_IN_BYTES 0x20000
#define NOR_FLASH_TFFS_BASE (AT91_FLASH_BASE + NOR_FLASH_TFFS_OFFSET)
#endif /* INCLUDE_NOR_FLASH */
#undef INCLUDE_FLASH /**Flash/NVRAM memory configuration**/
#ifdef INCLUDE_FLASH
#define FLASH_SIZE 0x00020000 /* one 128kbyte block of Flash*/
#define NV_RAM_SIZE 0x100 /* how much we use as NVRAM */
#undef NV_BOOT_OFFSET
#define NV_BOOT_OFFSET 0 /* bootline at start of NVRAM */
#define FLASH_NO_OVERLAY /* do not read-modify-write all of Flash */
#define INCLUDE_FLASH_SIB_FOOTER /* add a SIB footer to block */
#else /* INCLUDE_FLASH */
#define NV_RAM_SIZE NONE
#endif /* INCLUDE_FLASH */
/*********************************** SPI DATAFLASH *********************************************/
#undef INCLUDE_SPI_DATAFLASH_CARD /** Dataflash File system configuration **/
#define INCLUDE_SPI_DATAFLASH
/*********************************** PCMCIA Card *********************************************/
#undef INCLUDE_PCMCIA
#ifdef INCLUDE_PCMCIA
#define PCMCIA_SOCKS AT91_PCMCIA_MAX_SOCK
#define PCMCIA_MEMBASE AT91_PCMCIA_BASE(0)
#define PCIC_BASE_ADR AT91_PCMCIA_BASE(0)
#define PCIC_INT_VEC INUM_TO_IVEC(PCIC_INT_LVL)
#define PCIC_INT_LVL AT91C_ID_PIOB
#define CIS_RANGE_SIZE 0x400
#define CIS_MEM_START 0 /*AT91_PCMCIA_AT_BASE(0)*/
#define CIS_REG_START 0x400000 /*AT91_PCMCIA_CM_BASE(0)*/
#define CIS_MEM_STOP CIS_MEM_START+(AT91_PCMCIA_REG-1)
#define CIS_REG_STOP CIS_REG_START+(AT91_PCMCIA_REG-1)
#endif /* INCLUDE_PCMCIA */
/*********************************** DISPLAY *********************************************/
#undef INCLUDE_DISPLAY /** Display configuration **/
#ifdef INCLUDE_DISPLAY
#ifdef __EK__
#define S1D13806_BASE ( (unsigned char *) 0x40000000 )
#else
#define S1D13806_BASE ( (unsigned char *) 0x30000000 )
#endif
#endif /* INCLUDE_DISPLAY */
#undef INCLUDE_MMC /** MMC configuration **/
#undef INCLUDE_PCI /* PCI configuration */
/*********************************** WINDML *********************************************/
#ifdef INCLUDE_WINDML
#define INT_LVL_MOUSE INT_LVL_SPI
#define INT_LVL_KEYBOARD INT_LVL_IRQ0
#define INT_VEC_MOUSE INT_VEC_SPI
#define INT_VEC_KEYBOARD INT_VEC_IRQ0
#endif/* INCLUDE_WINDML */
/****************************************************************************************
Low Level Initialization
*******************************************************************************************/
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
#define CFG_USE_MAIN_OSCILLATOR 1
#define CFG_USE_PLLA 1
#undef CFG_USE_PLLB
/* flash */
#define MC_PUIA_VAL 0x00000000
#define MC_PUP_VAL 0x00000000
#define MC_PUER_VAL 0x00000000
#define MC_ASR_VAL 0x00000000
#define MC_AASR_VAL 0x00000000
#define EBI_CFGR_VAL 0x00000000
#define SMC2_CSR_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */
/* clocks */
#define PLLAR_VAL 0x20263E04 /* 179.712000 MHz for PCK */
#define PLLBR_VAL 0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */
#define MCKR_VAL 0x00000202 /* PCK/3 = MCK Master Clock = 59.904000MHz from PLLA */
/* sdram */
#define PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */
#define PIOC_BSR_VAL 0x00000000
#define PIOC_PDR_VAL 0xFFFF0000
#define EBI_CSA_VAL 0x0000000A /* CS1=SDRAM CS3=NANDFLASH*/
#define SDRC_CR_VAL 0x2188c155 /* set up the SDRAM */
#define SDRAM LOCAL_MEM_LOCAL_ADRS /* address of the SDRAM */
#define SDRAM1 (LOCAL_MEM_LOCAL_ADRS +0x80) /* address of the SDRAM */
#define SDRAM_VAL 0x00000000 /* value written to SDRAM */
#define SDRC_MR_VAL 0x00000002 /* Precharge All */
#define SDRC_MR_VAL1 0x00000004 /* refresh */
#define SDRC_MR_VAL2 0x00000003 /* Load Mode Register */
#define SDRC_MR_VAL3 0x00000000 /* Normal Mode */
#define SDRC_TR_VAL 0x000002E0 /* Write refresh rate */
/* nor flash */
#define SMC_CSR0_VAL 0x00003284
#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
#include "at91rm9200.h"
#ifndef __ASSEMBLER__
static __inline__ void AT91_CfgPIO_USART0(void) {
AT91_SYS->PIOA_PDR = AT91C_PA17_TXD0 | AT91C_PA18_RXD0
| AT91C_PA20_CTS0;
/*
* Errata #39 - RTS0 is not internally connected to PA21. We need to drive
* the pin manually. Default is off (RTS is active low).
*/
AT91_SYS->PIOA_PER = AT91C_PA21_RTS0;
AT91_SYS->PIOA_OER = AT91C_PA21_RTS0;
AT91_SYS->PIOA_SODR = AT91C_PA21_RTS0;
}
static __inline__ void AT91_CfgPIO_USART1(void) {
AT91_SYS->PIOB_PDR = AT91C_PB18_RI1 | AT91C_PB19_DTR1
| AT91C_PB20_TXD1 | AT91C_PB21_RXD1 | AT91C_PB23_DCD1
| AT91C_PB24_CTS1 | AT91C_PB25_DSR1 | AT91C_PB26_RTS1;
}
static __inline__ void AT91_CfgPIO_USART2(void) {
AT91_SYS->PIOA_PDR = AT91C_PA22_RXD2 | AT91C_PA23_TXD2;
}
static __inline__ void AT91_CfgPIO_USART3(void) {
AT91_SYS->PIOA_PDR = AT91C_PA5_TXD3 | AT91C_PA6_RXD3;
AT91_SYS->PIOA_BSR = AT91C_PA5_TXD3 | AT91C_PA6_RXD3;
}
static __inline__ void AT91_CfgPIO_DBGU(void) {
AT91_SYS->PIOA_PDR = AT91C_PA31_DTXD | AT91C_PA30_DRXD;
}
/*
* Configure Ethernet for RMII mode.
*/
static __inline__ void AT91_CfgPIO_EMAC_RMII(void) {
AT91_SYS->PIOA_PDR = AT91C_PA16_EMDIO | AT91C_PA15_EMDC | AT91C_PA14_ERXER | AT91C_PA13_ERX1
| AT91C_PA12_ERX0 | AT91C_PA11_ECRS_ECRSDV | AT91C_PA10_ETX1
| AT91C_PA9_ETX0 | AT91C_PA8_ETXEN | AT91C_PA7_ETXCK_EREFCK;
AT91_SYS->PIOB_PDR = AT91C_PB19_ERXCK;
AT91_SYS->PIOB_BSR = AT91C_PB19_ERXCK;
}
/*
* Configure Ethernet for MII mode.
*/
static __inline__ void AT91_CfgPIO_EMAC_MII(void) {
AT91_SYS->PIOA_PDR = AT91C_PA16_EMDIO | AT91C_PA15_EMDC | AT91C_PA14_ERXER | AT91C_PA13_ERX1
| AT91C_PA12_ERX0 | AT91C_PA11_ECRS_ECRSDV | AT91C_PA10_ETX1
| AT91C_PA9_ETX0 | AT91C_PA8_ETXEN | AT91C_PA7_ETXCK_EREFCK;
AT91_SYS->PIOB_PDR = AT91C_PB19_ERXCK | AT91C_PB18_ECOL | AT91C_PB17_ERXDV
| AT91C_PB16_ERX3 | AT91C_PB15_ERX2 | AT91C_PB14_ETXER | AT91C_PB13_ETX3
| AT91C_PB12_ETX2;
AT91_SYS->PIOB_BSR = AT91C_PB19_ERXCK | AT91C_PB18_ECOL | AT91C_PB17_ERXDV
| AT91C_PB16_ERX3 | AT91C_PB15_ERX2 | AT91C_PB14_ETXER | AT91C_PB13_ETX3
| AT91C_PB12_ETX2;
}
/*
* Configure interrupt from Ethernet PHY.
*/
static __inline__ void AT91_CfgPIO_EMAC_PHY(void) {
AT91_SYS->PMC_PCER = 1 << AT91C_ID_PIOC; /* enable peripheral clock */
#ifdef CONFIG_MACH_CSB337
AT91_SYS->PIOC_ODR = AT91C_PIO_PC2;
#else
AT91_SYS->PIOC_ODR = AT91C_PIO_PC4;
#endif
}
/*
* Enable the Two-Wire interface.
*/
static __inline__ void AT91_CfgPIO_TWI(void) {
AT91_SYS->PIOA_PDR = AT91C_PA25_TWD | AT91C_PA26_TWCK;
AT91_SYS->PIOA_ASR = AT91C_PA25_TWD | AT91C_PA26_TWCK;
AT91_SYS->PIOA_MDER = AT91C_PA25_TWD | AT91C_PA26_TWCK; /* open drain */
}
/*
* Enable the Serial Peripheral Interface.
*/
static __inline__ void AT91_CfgPIO_SPI(void) {
AT91_SYS->PIOA_PDR = AT91C_PA0_MISO | AT91C_PA1_MOSI | AT91C_PA2_SPCK;
}
static __inline__ void AT91_CfgPIO_SPI_CS0(void) {
AT91_SYS->PIOA_PDR = AT91C_PA3_NPCS0;
}
static __inline__ void AT91_CfgPIO_SPI_CS1(void) {
AT91_SYS->PIOA_PDR = AT91C_PA4_NPCS1;
}
static __inline__ void AT91_CfgPIO_SPI_CS2(void) {
AT91_SYS->PIOA_PDR = AT91C_PA5_NPCS2;
}
static __inline__ void AT91_CfgPIO_SPI_CS3(void) {
AT91_SYS->PIOA_PDR = AT91C_PA6_NPCS3;
}
/*
* Select the DataFlash card.
*/
static __inline__ void AT91_CfgPIO_DataFlashCard(void) {
AT91_SYS->PIOB_PER = AT91C_PIO_PB7;
AT91_SYS->PIOB_OER = AT91C_PIO_PB7;
AT91_SYS->PIOB_CODR = AT91C_PIO_PB7;
}
static __inline__ void AT91_CfgPIO_NAND(void) {
/*memory mapping structures */
#define SM_ID_RWH (5 << 28)
#define SM_RWH (1 << 28)
#define SM_RWS (0 << 24)
#define SM_TDF (1 << 8)
#define SM_NWS (3)
/* Setup Smart Media, fitst enable the address range of CS3
*AT91C_EBI_CSA |= AT91C_EBI_CS3A_SMC_SmartMedia;*/
/* set the bus interface characteristics based on
tDS Data Set up Time 30 - ns
tDH Data Hold Time 20 - ns
tALS ALE Set up Time 20 - ns
16ns at 60 MHz ~= 3 */
AT91C_BASE_SMC2->SMC2_CSR[3] = (SM_RWH | SM_RWS |
AT91C_SMC2_ACSS_STANDARD | AT91C_SMC2_DBW_8 |
SM_TDF | AT91C_SMC2_WSEN | SM_NWS);
#if 1
/* enable the SMOE line PC0=SMCE, A21=CLE, A22=ALE */
*AT91C_PIOC_ASR = AT91C_PC1_BFRDY_SMOE | AT91C_PC3_BFBAA_SMWE;
*AT91C_PIOC_PDR = AT91C_PC1_BFRDY_SMOE | AT91C_PC3_BFBAA_SMWE;
/* Configure PC0 as output */
*AT91C_PIOC_PER = AT91C_PIO_PC0; /* enable pio */
*AT91C_PIOC_OER = AT91C_PIO_PC0; /* enable output */
*AT91C_PIOC_SODR = AT91C_PIO_PC0;
/* Configure PC2 as input (signal READY of the SmartMedia) */
*AT91C_PIOC_PER = AT91C_PIO_PC2; /* enable direct output enable */
*AT91C_PIOC_ODR = AT91C_PIO_PC2; /* disable output */
/* pull up io ports */
*AT91C_PIOC_PPUER = (AT91C_PIO_PC0 | AT91C_PIO_PC2); /* internally pull up */
/* PIOB and PIOC clock enabling */
*AT91C_PMC_PCER = 1 << AT91C_ID_PIOB;
*AT91C_PMC_PCER = 1 << AT91C_ID_PIOC;
#else
/* enable the SMOE line PC0=SMCE, A21=CLE, A22=ALE */
*AT91C_PIOC_ASR = AT91C_PC0_BFCK | AT91C_PC1_BFRDY_SMOE |
AT91C_PC3_BFBAA_SMWE;
*AT91C_PIOC_PDR = AT91C_PC0_BFCK | AT91C_PC1_BFRDY_SMOE |
AT91C_PC3_BFBAA_SMWE;
/* Configure PC2 as input (signal READY of the SmartMedia) */
*AT91C_PIOC_PER = AT91C_PC2_BFAVD; /* enable direct output enable */
*AT91C_PIOC_ODR = AT91C_PC2_BFAVD; /* disable output */
/* Configure PB1 as input (signal Card Detect of the SmartMedia) */
*AT91C_PIOB_PER = AT91C_PIO_PB1; /* enable direct output enable */
*AT91C_PIOB_ODR = AT91C_PIO_PB1; /* disable output */
/* PIOB and PIOC clock enabling */
*AT91C_PMC_PCER = 1 << AT91C_ID_PIOB;
*AT91C_PMC_PCER = 1 << AT91C_ID_PIOC;
#endif
}
static __inline__ int AT91_PIO_SmartMedia_CardDetect(void) {
return (AT91_SYS->PIOB_PDSR & AT91C_PIO_PB1) ? 1 : 0;
}
#endif /* __ASSEMBLER__ */
#include "port.h"
#endif /* __AT91RM9200DK_H */