www.pudn.com > noc.rar > cache.h

#ifndef CACHE_H_INCLUDED
#define CACHE_H_INCLUDED

#include 

#include "cache_dim.h"
//#include "cache_memory.h"
#include "cache_bram.h"
#include "cache_ctrl.h"

SC_MODULE(DWORD_REG_SEL){
  sc_in clk, disable, select;
  sc_in< sc_bv > din;

  sc_out< sc_bv > dout;
  sc_out< sc_bv > dout_select;
  
  sc_signal< sc_bv > data;
  
  void reg(){
	if( !disable.read() ) 
	  data.write(din.read());
  }
  void out(){
	dout.write( data.read() );
	dout_select.write( select.read() ? data.read() : din.read() );
  }

  SC_CTOR(DWORD_REG_SEL){
	SC_METHOD(reg);
	sensitive_pos << clk;
	SC_METHOD(out);
	sensitive << select << data << din;
  }
};

SC_MODULE(REG2_SEL){
  sc_in clk, disable, select;
  sc_in< sc_bv<2> > din;

  sc_out< sc_bv<2> > dout;
  sc_out< sc_bv<2> > dout_select;
  
  sc_signal< sc_bv<2> > data;
  
  void reg(){
	if( !disable.read() ) 
	  data.write(din.read());
  }
  void out(){
	dout.write( data.read() );
	dout_select.write( select.read() ? data.read() : din.read() );
  }

  SC_CTOR(REG2_SEL){
	SC_METHOD(reg);
	sensitive_pos << clk;
	SC_METHOD(out);
	sensitive << select << data << din;
  }
};

SC_MODULE(MEM_BUFFER){
  sc_in< sc_bv<32> > din, addrin;
  sc_out< sc_bv<32> > dout, addrout;
  
  void out(){
	dout.write( din.read() );
	addrout.write( addrin.read() );
  }
  SC_CTOR(MEM_BUFFER){
	SC_METHOD(out);
	sensitive << din << addrin;
  }
};

SC_MODULE(REG_DISABLE){
  sc_in< bool > memwait;
  sc_in< sc_bv<1> > en;
  sc_out< bool > disable;
  
  SC_CTOR(REG_DISABLE){
	SC_METHOD(out);
	sensitive << memwait << en;
  }
  
  void out(){
	disable.write( memwait.read() || (en.read()[0]==false) );
  }
};

SC_MODULE(DATA_CACHE)
{  
  sc_in < sc_bv > addr;
  sc_in< sc_bv > din;
  sc_out< sc_bv > dout;
  sc_out< bool > memwait;
  sc_in< sc_bv > w;
  sc_in< sc_bv > r;
  sc_in< bool > clk;
  sc_in< sc_bv<1> > en;
  
  sc_out< sc_bv<32> > mem_addr, mem_din;
  sc_in< sc_bv<32> > mem_dout;
  sc_out< bool > mem_ww, mem_wb, mem_r;
  sc_in< bool > mem_rdy;

  CACHE_MEMORY *cache_memory;
  CACHE_DIN_SELECT *din_select;
  CACHE_ADDR_SPLIT *addr_split;
  CACHE_BYTE_SELECT *byte_select;
  CACHE_MISS_CTRL *miss_ctrl;
  

  DWORD_REG_SEL *addr_register, *data_register;
  REG2_SEL *r_register, *w_register;
  REG_DISABLE *register_disable;
  
  sc_signal< sc_bv<32> > din_reg, addr_reg;
  sc_signal< bool > current_reg;
  sc_signal< sc_bv<32> > data_current, addr_current;
  
  sc_signal< sc_bv<32> > data_mem_in, data_fetch_out, data_mem_out;
  
  sc_signal< sc_bv > tag_in, tag_out, tag_reg;
  sc_signal< sc_bv > index, index_reg;
  sc_signal< sc_bv > offset, offset_reg;
  sc_signal< sc_uint<2> > byte, byte_reg;
  sc_signal< bool > cache_en, cache_we;
  sc_signal< bool > valid, valid_select;
  sc_signal< bool > fetch, storew, storeb, fetch_busy;
  sc_signal< sc_uint<2> > fetch_word;
  sc_signal< bool > fetch_word_rdy;
  sc_signal< bool > rewrite, byte_rpl;
  sc_signal< sc_bv > w_reg, w_current;
  sc_signal< sc_bv > r_reg, r_current;
  sc_signal< bool > reg_disable;
  
  SC_CTOR(DATA_CACHE)
	{
	  cache_memory = new CACHE_MEMORY("cache_memory");
	  din_select = new CACHE_DIN_SELECT("din_select");
	  addr_split = new CACHE_ADDR_SPLIT("addr_split");
	  byte_select = new CACHE_BYTE_SELECT("byte_select");
	  miss_ctrl = new CACHE_MISS_CTRL("miss_ctrl");
	  addr_register = new DWORD_REG_SEL("addr_register");
	  data_register = new DWORD_REG_SEL("data_register");
	  r_register = new REG2_SEL("r_register");
	  w_register = new REG2_SEL("w_register");
	  register_disable = new REG_DISABLE("register_disable");
	  
	  register_disable->en(en);
	  register_disable->memwait(memwait);
	  register_disable->disable(reg_disable);
	  
	  addr_register->din(addr);
	  addr_register->dout(addr_reg);
	  addr_register->dout_select(addr_current);
	  addr_register->clk(clk);
	  addr_register->disable(reg_disable);
	  addr_register->select(current_reg);

	  data_register->din(din);
	  data_register->dout(din_reg);
	  data_register->dout_select(data_current);
	  data_register->clk(clk);
	  data_register->disable(reg_disable);
	  data_register->select(current_reg);

	  r_register->din(r);
	  r_register->dout(r_reg);
	  r_register->dout_select(r_current);
	  r_register->clk(clk);
	  r_register->disable(reg_disable);
	  r_register->select(current_reg);

	  w_register->din(w);
	  w_register->dout(w_reg);
	  w_register->dout_select(w_current);
	  w_register->clk(clk);
	  w_register->disable(reg_disable);
	  w_register->select(current_reg);

	  cache_memory->clk(clk);
	  cache_memory->din(data_mem_in);
	  cache_memory->valid_in(valid_select);
	  cache_memory->tagi(tag_in);
	  cache_memory->index(index);
	  cache_memory->offset(offset);

	  cache_memory->en(cache_en);
	  cache_memory->we(cache_we);
	  cache_memory->tago(tag_out);
	  cache_memory->dout(data_mem_out);
	  cache_memory->valid(valid);
	  	  
	  din_select->din_data(data_current);
	  din_select->din_data_reg(din_reg);
	  // din_select->din_fetch(data_fetch_out);
	  din_select->din_fetch(mem_dout);
	  din_select->din_out(data_mem_out);
	  din_select->w(w);
	  din_select->byte(byte);
	  din_select->fetch_word_rdy(fetch_word_rdy);
	  din_select->rewrite(rewrite);
	  din_select->byte_rpl(byte_rpl);
	  din_select->data(data_mem_in);
	  din_select->valid(valid_select);
	  din_select->rewrite_valid(valid);
	  
	  addr_split->addr(addr_current);	  	 
	  addr_split->addr_reg(addr_reg);	  	 
	  addr_split->tag(tag_in);
	  addr_split->index(index);
	  addr_split->offset(offset);
	  addr_split->byte(byte);
	  addr_split->tag_reg(tag_reg);
	  addr_split->index_reg(index_reg);
	  addr_split->offset_reg(offset_reg);
	  addr_split->byte_reg(byte_reg);
	  addr_split->fetch_word( fetch_word );
	  addr_split->fetch_word_rdy( fetch_word_rdy );
	  addr_split->rewrite(rewrite);
	  addr_split->tag_rewrite(tag_out);
		
	  byte_select->din(data_mem_out);
	  byte_select->byte(byte_reg);
	  byte_select->r(r_reg);
	  byte_select->dout(dout);
	  
	  miss_ctrl->clk(clk);
	  miss_ctrl->en(en);
	  miss_ctrl->cache_valid(valid);
	  miss_ctrl->cache_tag(tag_out);
	  miss_ctrl->addr_tag(tag_reg);
	  miss_ctrl->miss_wait(memwait);
	  miss_ctrl->fetch_word(fetch_word);
	  miss_ctrl->fetch_word_rdy(fetch_word_rdy);
	  miss_ctrl->w(w);
	  miss_ctrl->r(r);
	  miss_ctrl->cache_we(cache_we);
	  miss_ctrl->cache_en(cache_en);
	  miss_ctrl->rewrite(rewrite);
	  miss_ctrl->byte_rpl(byte_rpl);
	  miss_ctrl->current_reg(current_reg);

	  miss_ctrl->mem_wb(mem_wb);
	  miss_ctrl->mem_ww(mem_ww);
	  miss_ctrl->mem_r(mem_r);
	  miss_ctrl->mem_rdy(mem_rdy);
	  miss_ctrl->din( data_current );
	  miss_ctrl->addr( addr_current );
	  miss_ctrl->mem_din( mem_din );
	  miss_ctrl->mem_addr( mem_addr );
	  
	}
};


#endif