www.pudn.com > noc.rar > bregisterfile16.h

/*
 *  TU Eindhoven
 *  Eindhoven, The Netherlands
 *
 *  Name            :   bregisterfile16.h
 *
 *  Author          :   A.S.Slusarczyk@tue.nl
 *
 *  Date            :   
 *
 *  Function        :   Xilinx-Block-RAM-based register file
 *
 *
 */
  
#ifndef BREGISTERFILE16_H_INCLUDED
#define BREGISTERFILE16_H_INCLUDED

#include "mips.h"
#include "xlxram.h"

SC_MODULE(BRAM512x32_CONV) {
  
	sc_in< 	sc_bv	>	r_addr;
	sc_out< sc_bv 	>	r_data;
	
	sc_in< 	sc_bv	>	w_addr;
	sc_in< 	sc_bv 	>	w_data;
	sc_in<  sc_bv<1>  >         w;
	sc_in<	bool		    >   clk;

	sc_in > DOA;
	sc_in > DOPA;
	sc_out > ADDRA;
	sc_out > DIA;
	sc_out > DIPA;
	sc_out ENA;
	sc_out CLKA;
	sc_out WEA;
	sc_out SSRA;

	sc_in > DOB;
	sc_in > DOPB;
	sc_out > ADDRB;
	sc_out > DIB;
	sc_out > DIPB;
	sc_out ENB;
	sc_out CLKB;
	sc_out WEB;
	sc_out SSRB;

	void clock();
	void out();
	void in();
	
	SC_CTOR(BRAM512x32_CONV) {
	  SC_METHOD(in);
	  sensitive << r_addr << w_addr << w_data << w ;
	  
	  SC_METHOD(clock);
	  sensitive << clk;
		
	  SC_METHOD(out);
	  sensitive << DOA << DOB << DOPA << DOPB; 

	};
	
};

// 512x32 memory with separate read/write ports
SC_MODULE(BRAM512x32)
{
	sc_in< 	sc_bv	>	r_addr;
	sc_out< sc_bv 	>	r_data;
	
	sc_in< 	sc_bv	>	w_addr;
	sc_in< 	sc_bv 	>	w_data;
	sc_in<  sc_bv<1>  >         w;
	sc_in<	bool		    >   clk;

	RAMB16_S36_S36 *bram;
	BRAM512x32_CONV *conv;
	
	sc_signal > DOA;
	sc_signal > ADDRA;
	sc_signal > DIA;
	sc_signal ENA;
	sc_signal CLKA;
	sc_signal WEA;
	sc_signal SSRA;
	sc_signal > DOPA, DIPA;

	sc_signal > DOB;
	sc_signal > ADDRB;
	sc_signal > DIB;
	sc_signal ENB;
	sc_signal CLKB;
	sc_signal WEB;
	sc_signal SSRB;
	sc_signal > DOPB, DIPB;
	
	SC_CTOR(BRAM512x32) {
	  bram = new RAMB16_S36_S36("bramh");
	  conv = new BRAM512x32_CONV("conv");
	  
	  bram->ADDRA(ADDRA);
	  conv->ADDRA(ADDRA);
	  bram->ADDRB(ADDRB);
	  conv->ADDRB(ADDRB);
	  
	  bram->DIA(DIA);
	  conv->DIA(DIA);
	  bram->DIB(DIB);
	  conv->DIB(DIB);
	  
	  bram->DOA(DOA);
	  conv->DOA(DOA);
	  bram->DOB(DOB);
	  conv->DOB(DOB);

	  bram->DOPA(DOPA);
	  conv->DOPA(DOPA);
	  bram->DOPB(DOPB);
	  conv->DOPB(DOPB);
	  bram->DIPA(DIPA);
	  conv->DIPA(DIPA);
	  bram->DIPB(DIPB);
	  conv->DIPB(DIPB);

	  bram->CLKA(CLKA);
	  conv->CLKA(CLKA);
	  bram->CLKB(CLKB);
	  conv->CLKB(CLKB);
	  
	  bram->ENA(ENA);
	  conv->ENA(ENA);
	  bram->ENB(ENB);
	  conv->ENB(ENB);
	  
	  bram->WEA(WEA);
	  conv->WEA(WEA);
	  bram->WEB(WEB);
	  conv->WEB(WEB);
	  
	  bram->SSRA(SSRA);
	  conv->SSRA(SSRA);
	  bram->SSRB(SSRB);
	  conv->SSRB(SSRB);
	  
	  
	  conv->r_addr(r_addr);
	  conv->r_data(r_data);
	  conv->w_data(w_data);
	  conv->w_addr(w_addr);
	  conv->w(w);
	  conv->clk(clk);
	  
	};
  
};

	 

// register file module with original interface
SC_MODULE(REGFILE16) {
	sc_in< 	sc_bv	>	r_addr_reg1;
	sc_out< sc_bv 	>	r_data_reg1;

	sc_in< 	sc_bv	>	r_addr_reg2;
	sc_out< sc_bv 	>	r_data_reg2;
	
	sc_in< 	sc_bv	>	w_addr_reg;
	sc_in< 	sc_bv 	>	w_data_reg;
	sc_in< 	sc_bv<1>	 	>	w;
	
	
	sc_in< 	bool > clk;
	//	sc_in< 	bool > rst;
	
	BRAM512x32 *regs1, *regs2;
		
	SC_CTOR(REGFILE16) {
	  regs1 = new BRAM512x32("regs1");
	  regs2 = new BRAM512x32("regs2");
	  
	  regs1->r_addr(r_addr_reg1);
	  regs1->r_data(r_data_reg1);
	  regs1->w_data(w_data_reg);
	  regs1->w_addr(w_addr_reg);
	  regs1->w(w);
	  regs1->clk(clk);

	  regs2->r_addr(r_addr_reg2);
	  regs2->r_data(r_data_reg2);
	  regs2->w_data(w_data_reg);
	  regs2->w_addr(w_addr_reg);
	  regs2->w(w);
	  regs2->clk(clk);
	  
	};
};


#endif